IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY
CLOCK BUFFER
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IDT2305
Phase-Lock Loop Clock Distribution
10MHz to 133MHz operating frequency
Distributes one clock input to one bank of five outputs
Zero Input-Output Delay
Output Skew < 250ps
Low jitter <200 ps cycle-to-cycle
IDT2305-1 for Standard Drive
IDT2305-1H for High Drive
No external RC network required
Operates at 3.3V V
DD
Power down mode
Available in SOIC package
DESCRIPTION:
The IDT2305 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT2305 is an 8-pin version of the IDT2309. IDT2305 accepts one
reference input, and drives out five low skew clocks. The -1H version of this
device operates, up to 133MHz frequency and has a higher drive than the
-1 device. All parts have on-chip PLLs which lock to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT2305 enters power down. In
this mode, the device will draw less than 25
μA,
the outputs are tri-stated,
and the PLL is not running, resulting in a significant reduction of power.
The IDT2305 is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
8
CLKOUT
PLL
REF
1
Control
Logic
3
CLK1
2
CLK2
5
CLK3
7
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2007
Integrated Device Technology, Inc.
DECEMBER 2007
DSC 5174/8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
