IDT54/74FCT3244/A
3.3V CMOS OCTAL BUFFER/LINE DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
6V
V
CC
SWITCH POSITION
Open
GND
500
Ω
V
Pulse
Generator
R
T
IN
V
D.U.T.
OUT
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
6V
50pF
C
L
500
Ω
SET-UP, HOLD AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
SU
t
H
t
REM
t
SU
t
H
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
2779 drw 06
←
GND
Open
2779 lnk 08
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2779 drw 03
PULSE WIDTH
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
2779 drw 04
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
1.5V
1.5V
2779 drw 05
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY SWITCH
6V
LOW
t
PZH
OUTPUT
NORMALLY
HIGH
SWITCH
GND
3V
1.5V
t
PHZ
0.3V
1.5V
0V
V
OH
0V
2779 drw 07
DISABLE
3V
1.5V
t
PLZ
0V
3V
0.3V
V
OL
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
3. If V
CC
is below 3V, input voltage swings should be adjusted not to exceed
V
CC
.
8.11
5
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
