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IDT6116SA45P 参数 Datasheet PDF下载

IDT6116SA45P图片预览
型号: IDT6116SA45P
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS静态RAM 16K ( 2K ×8位) [CMOS STATIC RAM 16K (2K x 8 BIT)]
分类和应用:
文件页数/大小: 10 页 / 95 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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CMOS STATIC RAM
16K (2K x 8 BIT)
Integrated Device Technology, Inc.
IDT6116SA
IDT6116LA
FEATURES:
• High-speed access and chip select times
— Military: 20/25/35/45/55/70/90/120/150ns (max.)
— Commercial: 15/20/25/35/45ns (max.)
• Low-power consumption
• Battery backup operation
— 2V data retention voltage (LA version only)
• Produced with advanced CMOS high-performance
technology
• CMOS process virtually eliminates alpha particle
soft-error rates
• Input and output directly TTL-compatible
• Static operation: no clocks or refresh required
• Available in ceramic and plastic 24-pin DIP, 24-pin Thin
Dip and 24-pin SOIC and 24-pin SOJ
• Military product compliant to MIL-STD-833, Class B
DESCRIPTION:
The IDT6116SA/LA is a 16,384-bit high-speed static RAM
organized as 2K x 8. It is fabricated using IDT's high-perfor-
mance, high-reliability CMOS technology.
Access times as fast as 15ns are available. The circuit also
offers a reduced power standby mode. When
CS
goes HIGH,
the circuit will automatically go to, and remain in, a standby
power mode, as long as
CS
remains HIGH. This capability
provides significant system level power and cooling savings.
The low-power (LA) version also offers a battery backup data
retention capability where the circuit typically consumes only
1µW to 4µW operating off a 2V battery.
All inputs and outputs of the IDT6116SA/LA are TTL-
compatible. Fully static asynchronous circuitry is used, requir-
ing no clocks or refreshing for operation.
The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil
plastic or ceramic DIP and a 24-lead gull-wing SOIC, and a 24
-lead J-bend SOJ providing high board-level packing densi-
ties.
Military grade product is manufactured in compliance to the
latest version of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A
0
V
CC
ADDRESS
DECODER
A
10
128 X 128
MEMORY
ARRAY
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
CS
OE
WE
CONTROL
CIRCUIT
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The IDT logo is aregistered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MARCH 1996
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