欢迎访问ic37.com |
会员登录 免费注册
发布采购

IDT7006S25PF 参数 Datasheet PDF下载

IDT7006S25PF图片预览
型号: IDT7006S25PF
PDF下载: 下载PDF文件 查看货源
内容描述: 高速16K ×8双端口静态RAM [HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 20 页 / 262 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
 浏览型号IDT7006S25PF的Datasheet PDF文件第2页浏览型号IDT7006S25PF的Datasheet PDF文件第3页浏览型号IDT7006S25PF的Datasheet PDF文件第4页浏览型号IDT7006S25PF的Datasheet PDF文件第5页浏览型号IDT7006S25PF的Datasheet PDF文件第6页浏览型号IDT7006S25PF的Datasheet PDF文件第7页浏览型号IDT7006S25PF的Datasheet PDF文件第8页浏览型号IDT7006S25PF的Datasheet PDF文件第9页  
HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT7006S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
— IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
— IDT7006L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• IDT7006 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/
S
= H for
BUSY
output flag on Master,
M/
S
= L for
BUSY
input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in a 68-pin PGA, a 68-pin quad flatpack, a 68-
pin PLCC, and a 64-pin TQFP
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT7006 is a high-speed 16K x 8 Dual-Port Static
RAM. The IDT7006 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
FUNCTIONAL BLOCK DIAGRAM
OE
L
R/
OE
R
R/
CE
L
W
L
CE
R
W
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
14
(1,2)
A
13L
A
0L
MEMORY
ARRAY
Address
Decoder
A
13R
A
0R
NOTES:
1. (MASTER):
BUSY
is
output;
(SLAVE):
BUSY
is input.
2.
BUSY
outputs
and
INT
outputs are
non-tri-stated
push-pull.
14
OE
L
R/
CE
L
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
R/
OE
R
W
R
SEM
R
(2)
SEM
L
INT
L
(2)
M/
S
INT
R
2739 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2739/5
6.07
1