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IDT70121L25J 参数 Datasheet PDF下载

IDT70121L25J图片预览
型号: IDT70121L25J
PDF下载: 下载PDF文件 查看货源
内容描述: HIGH -SPEED 2K ×9双端口静态繁忙和中断RAM [HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT]
分类和应用:
文件页数/大小: 12 页 / 170 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM WITH BUSY & INTERRUPT
Integrated Device Technology, Inc.
IDT70121S/L
IDT70125S/L
FEATURES:
• High-speed access
– Commercial: 25/35/45/55ns (max.)
• Low-power operation
– IDT70121/70125S
Active: 500mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asychronous operation from either port
• MASTER IDT70121 easily expands data bus width to 18
bits or more using SLAVE IDT70125 chip
• On-chip port arbitration logic (IDT70121 only)
BUSY
output flag on Master;
BUSY
input on Slave
INT
flag for port-to-port communication
• Battery backup operation—2V data retention
• TTL-compatible, signal 5V (±10%) power supply
• Available in 52-pin PLCC
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT70121/IDT70125 are high-speed 2K x 9 Dual-Port
Static RAMs. The IDT70121 is designed to be used as a
stand-alone 9-bit Dual-Port RAM or as a “MASTER” Dual-Port
RAM together with the IDT70125 “SLAVE” Dual-Port in 18-
bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 18-bit-or-wider memory
system applications results in full-speed, error-free operation
without the need for additional discrete logic.
Both devices provide two independent ports with separate
control, address, and I/O pins that permit independent, asyn-
chronous access for reads or writes to any location in memory.
An automatic power-down feature, controlled by
CE
, permits
the on-chip circuitry of each port to enter a very low standby
power mode.
The IDT70121/IDT70125 utilizes a 9-bit wide data path to
allow for Data/Control and parity bits at the user’s option. This
feature is especially useful in data communications
applications where it is necessary to use a parity bit for
transmission/reception error checking.
FUNCTIONAL BLOCK DIAGRAM
OE
L
CE
L
R/
W
L
OE
R
R/
W
R
CE
R
I/O
0L
- I/O
8L
I/O
Control
I/O
Control
I/O
0R
-I/O
8R
BUSY
L
(1,2)
BUSY
R
Address
Decoder
11
(1,2)
A
10L
A
0L
MEMORY
ARRAY
Address
Decoder
A
11R
A
0R
11
NOTES:
1. 70121 (MASTER):
BUSY
is non-tri-
stated push-pull
output.
70125 (SLAVE):
BUSY
is input.
2.
INT
is totem-pole
output.
CE
L
OE
L
R/
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
INT
L(2)
INT
R
2654 drw 01
(2)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2654/4
6.10
1