IDT 70121/70125S/L
HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CE
CONTROLLED TIMING
(1,5)
t
WC
ADDRESS
t
AW
CE
t
AS
R/
(6)
t
EW
(2)
t
WR
(3)
W
t
DW
t
DH
DATA
IN
2654 drw 08
NOTES:
1. R/
W
or
CE
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a
CE
= V
IL
and a R/
W
= V
IL
3. t
WR
is measured from the earlier of
CE
or R/
W
going High to the end of the write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (
CE
or R/
W
) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If
OE
is low during a R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off
data to be placed on the bus for the required t
DW
. If
OE
is High during a R/
W
controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified t
WP
.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(6)
70121X25
70125X25
70121X35
70125X35
70121X45
70125X45
70121X55
70125X55
Symbol
Parameter
Busy Timing
(For Master IDT70121 Only)
t
BAA
t
BDA
t
BAC
t
BDC
t
WDD
t
DDD
t
APS
t
BDD
t
WH
t
WB
t
WH
t
WDD
t
DDD
Min. Max. Min. Max. Min. Max. Min. Max. Unit
—
—
—
—
—
(1)
BUSY
Access Time from Address
BUSY
Disable Time from Address
BUSY
Access Time from Chip Enable
BUSY
Disable Time from Chip Enable
Write Pulse to Data Delay
(1)
20
20
20
20
50
35
—
30
—
—
—
50
35
—
—
—
—
—
—
5
—
20
0
20
—
—
20
20
20
20
60
45
—
30
—
—
—
60
45
—
—
—
—
—
—
5
—
20
0
20
—
—
20
20
20
20
70
55
—
35
—
—
—
70
55
—
—
—
—
—
—
5
—
20
0
20
—
—
30
30
30
30
80
65
—
45
—
—
—
80
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Data Valid to Read Data Delay
Arbitration Priority Set-up Time
(2)
—
5
—
15
0
15
BUSY
Disable to Valid Data
(3)
Write Hold After
BUSY
(5)
Write to
BUSY
Input
(4)
Write Hold After
BUSY
(5)
Write Pulse to Data Delay
(1)
(1)
Busy Timing
(For Slave IDT70125 Only)
—
—
Write Data Valid to Read Data Delay
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and
BUSY
“.
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. “X” in part numbers indicates power rating (S or L).
2654 tbl 10
6.10
7
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
