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IDT7025S25J 参数 Datasheet PDF下载

IDT7025S25J图片预览
型号: IDT7025S25J
PDF下载: 下载PDF文件 查看货源
内容描述: 高速8K ×16双口静态RAM [HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM]
分类和应用:
文件页数/大小: 20 页 / 294 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5V
5V
1250Ω
DATA
OUT
1250Ω
DATA
OUT
775Ω
30pF
775Ω
5pF
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
2683 tbl 12
BUSY
INT
2683 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
( for t
LZ
, t
HZ
, t
WZ
, t
OW
)
*
including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(4)
Symbol
READ CYCLE
t
RC
t
AA
t
ACE
t
ABE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
t
SOP
t
SAA
Read Cycle Time
Address Access Time
Chip Enable Access Time
(3)
Byte Enable Access Time
(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1, 2)
Output High-Z Time
(1, 2)
Chip Enable to Power Up Time
(1,2)
(1,2)
Parameter
IDT7025X15
Com'l. Only
Min. Max.
15
3
3
0
10
15
15
15
10
10
15
15
IDT7025X17
Com'l. Only
Min.
Max.
17
3
3
0
10
17
17
17
10
10
17
17
IDT7025X20
Min.
20
3
3
0
10
Max.
20
20
20
12
12
20
20
IDT7025X25
Min.
25
3
3
0
10
Max.
25
25
25
13
15
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Disable to Power Down Time
Semaphore Address Access
(3)
Semaphore Flag Update Pulse (
OE
or
SEM
)
IDT7025X35
Symbol
READ CYCLE
t
RC
t
AA
t
ACE
t
ABE
t
AOE
t
OH
t
LZ
t
HZ
t
PU
t
PD
t
SOP
t
SAA
Read Cycle Time
Address Access Time
Chip Enable Access Time
(3)
Byte Enable Access Time
(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1, 2)
Output High-Z Time
(1, 2)
Chip Enable to Power Up Time
(1,2)
(1,2)
IDT7025X55
Min.
55
3
3
0
15
Max.
55
55
55
30
25
50
55
Parameter
Min.
35
3
3
0
15
Max.
35
35
35
20
15
35
35
IDT7025X70
Mil. Only
Min.
Max.
70
3
3
0
15
70
70
70
35
30
50
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2683 tbl 13
Chip Disable to Power Down Time
Semaphore Address Access Time
Semaphore Flag Update Pulse (
OE
or
SEM
)
(3)
NOTES:
1. Transition is measured
±500mV
from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM,
CE
= V
IL,
UB
or
LB
= V
IL, and
SEM
= V
IH.
To access semephore,
CE
= V
IH or
UB
&
LB
= V
IH, and
4. "X" in part numbers indicates power rating (S or L).
6.16
SEM
= V
IL.
7