HIGH-SPEED 3.3V
4K x 16 DUAL-PORT
STATIC RAM
Features
x
x
x
IDT70V24S/L
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
Low-power operation
– IDT70V24S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V24L
Active: 380mW (typ.)
Standby: 660
µ
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
x
x
x
x
x
x
x
x
IDT70V24 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
(1,2)
BUSY
R
(1,2)
Address
Decoder
12
L
A
11L
A
0L
MEMORY
ARRAY
12
Address
Decoder
A
11R
A
0R
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
INT
R
(2)
2911 drw 01
M/
S
MARCH 2000
1
DSC-2911/8
©2000 Integrated Device Technology, Inc.
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
