IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT)
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 5, 7)
t
WC
ADDRESS
t
AW
CS1
t
CW
CS2
t
AS
WE
t
WR
t
WP
(7)
(3)
t
WHZ
DATA
OUT
(4)
(6)
t
OW
HIGH IMPEDANCE
t
DH
t
DW
(6)
t
CHZ
(6)
(4)
DATA
IN
DATA
IN
VALID
2964 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS1
AND CS2 CONTROLLED TIMING)
(1, 2, 5)
t
WC
ADDRESS
t
AW
CS1
CS2
t
AS
WE
t
CW
t
WR
(3)
t
DW
DATA
IN
DATA
IN
VALID
t
DH
2964 drw 10
NOTES:
1.
WE
must be HIGH,
CS1
must be HIGH, or CS2 must be LOW during all address transitions.
2. A write occurs during the overlap of a LOW
CS1
, HIGH CS2, and a LOW
WE
.
3. t
WR
is measured from the earlier of either
CS1
or
WE
going HIGH or CS2 going LOW to the end of the write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS1
LOW transition or the CS2 HIGH transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high impedance
state.
CS1
and CS2 must both be active during the t
CW
write period.
6. Transition is measured
±200mV
from steady state.
7.
OE
is continuously HIGH. During a
WE
controlled write cycle with
OE
LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to
turn off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the
minimum write pulse is the specified t
WP
.
7
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
