IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT)
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
t
RC
ADDRESS
t
AA
OE
t
OE
CS1
t
OLZ
(5)
CS2
t
CLZ
(5)
DATA
OUT
Vcc
SUPPLY
CURRENT
Icc
Isb
t
ACS
(3)
t
OHZ
(5)
t
CHZ
(5)
DATA
OUT
VALID
t
PD
HIGH IMPEDANCE
t
PU
2964 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2
(1, 2, 4)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
2964 drw 07
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS1
is LOW, CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of
CS1
transition LOW and CS2 transition HIGH; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured
±200mV
from steady state.
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
