IDT71028
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO.1 (
WE
CONTROLLED TIMING)
(1,2,3,5)
t
WC
ADDRESS
t
AW
CS
t
AS
WE
t
WP(3)
t
WR
t
WHZ
DATA
OUT
(4)
(6)
t
OW
HIGH IMPEDANCE
t
DW
t
DH
(6)
t
CHZ
(4)
(6)
DATA
IN
DATA
IN
VALID
2966 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.2 (
CS
CONTROLLED TIMING)
(1,2,5)
t
WC
ADDRESS
t
AW
CS
t
AS
WE
t
CW
t
WR
t
DW
DATA
IN
DATA
IN
VALID
t
DH
2966 drw 08
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3.
OE
is continuously HIGH. If during a
WE
controlled write cycle
OE
is LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to turn
off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified t
WP
.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured
±200mV
from steady state.
9.4
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
