IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and
BUSY
(2,3,4)
t
WC
ADDR
"A"
MATCH
t
WP
R/W
"A"
t
DW
DATA
IN"A"
t
APS
(1)
ADDR
"B"
t
BAA
BUSY
"B"
t
WDD
DATA
OUT"B"
t
DDD
NOTES:
1. To ensure that the earlier of the two ports wins.
t
APS
is ignored for Slave (IDT7142).
2.
CE
L
=
CE
R
= V
IL
3.
OE
= V
IL
for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
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t
DH
VALID
MATCH
t
BDA
t
BDD
VALID
Timing Waveform of Write with
BUSY
(4)
t
WP
R/W
"A"
t
WB
(3)
BUSY
"B"
t
WH
(1)
R/W
"B"
(2)
,
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NOTES:
1.
t
WH
must be met for both
BUSY
Input (IDT7142, slave) or Output (IDT7132, master).
2.
BUSY
is asserted on port "B" blocking R/W
"B"
, until
BUSY
"B"
goes HIGH.
3. t
WB
applies only to the slave version (IDT7142).
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
