IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(6)
7133X20
7143X20
Com'l Only
Symbol
BUSY
TIMING (For MASTER 71V33)
t
BAA
t
BDA
t
BAC
t
BDC
t
WDD
t
DDD
t
BDD
t
APS
t
WH
BUSY
Access Time from Address
BUSY
Disable Time from Address
BUSY
Access Time from Chip Enable
BUSY
Disable Time from Chip Enable
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
BUSY
Disable to Valid Data
(2)
Arbitration Priority Set-up Time
(3)
Write Hold After
BUSY
(5)
____
7133X25
7143X25
Com'l, Ind
& Military
Min.
Max.
7133X35
7143X35
Com'l, Ind
& Military
Min.
Max.
Unit
Parameter
Min.
Max.
20
20
20
17
40
30
25
____
____
____
20
20
20
20
50
35
30
____
____
____
30
30
25
25
60
45
35
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
5
20
5
20
5
25
BUSY
INPUT TIMING (For SLAVE 71V43)
t
WB
t
WH
t
WDD
t
DDD
BUSY
Input to Write
(4)
Write Hold After
BUSY
(5)
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
0
20
____
____
____
____
0
20
____
____
____
____
0
25
____
____
____
____
ns
ns
ns
ns
2746 tbl 12a
40
30
50
35
60
45
7133X45
7143X45
Com'l &
Military
Symbol
BUSY
TIMING (For MASTER 71V33)
t
BAA
t
BDA
t
BAC
t
BDC
t
WDD
t
DDD
t
BDD
t
APS
t
WH
BUSY
Access Time from Address
BUSY
Disable Time from Address
BUSY
Access Time from Chip Enable
BUSY
Disable Time from Chip Enable
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
BUSY
Disable to Valid Data
(2)
Arbitration Priority Set-up Time
(3)
Write Hold After
BUSY
(5)
____
7133X55
7143X55
Com'l, Ind
& Military
Min.
Max.
7133X70/90
7143X70/90
Com'l &
Military
Min.
Max.
Unit
Parameter
Min.
Max.
40
40
30
25
80
55
40
____
____
____
40
40
35
30
80
55
40
____
____
____
45/45
45/45
35/35
30/30
90/90
70/70
40/40
____
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
5
30
5
30
5/5
30/30
BUSY
INPUT TIMING (For SLAVE 71V43)
t
WB
t
WH
t
WDD
t
DDD
BUSY
Input to Write
(4)
Write Hold After
BUSY
(5)
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
0
30
____
____
____
____
0
30
____
____
____
____
0/0
30/30
____
____
____
____
ns
ns
ns
ns
2746 tbl 12b
80
55
80
55
90/90
70/70
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy".
2. t
BDD
is calculated parameter and is greater of 0, t
WDD
- t
WP
(actual) or t
DDD
- t
DW
(actual).
3. To ensure that the earlier of the two ports wins.
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (SA or LA).
6.42
10
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
