HIGH-SPEED 3.3V
1K X 8 DUAL-PORT
STATIC RAM
Features
x
x
IDT71V30S/L
High-speed access
– Commercial: 25/35/55ns (max.)
Low-power operation
– IDT71V30S
—
Active: 375mW (typ.)
—
Standby: 5mW (typ.)
– IDT71V30L
—
Active: 375mW (typ.)
—
Standby: 1mW (typ.)
x
x
x
x
x
x
On-chip port arbitration logic
Interrupt flags for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation, 2V data retention (L Only)
TTL-compatible, single 3.3V ±0.3V power supply
Industrial temperature range (-40
O
C to +85
O
C) is available
for selected speeds
Functional Block Diagram
OE
L
CE
L
R/
W
L
OE
R
CE
R
R/
W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
(1)
A
9L
A
0L
Address
Decoder
10
MEMORY
ARRAY
10
Address
Decoder
A
9R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
3741 drw 01
(2)
NOTES:
1. IDT71V30:
BUSY
outputs are non-tristatable push-pulls.
2.
INT
outputs are non-tristable push-pull output structure.
JANUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC 3741/7
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
