64K x 32
3.3V Synchronous SRAM
Flow-Through Outputs
Burst Counter, Single Cycle Deselect
Features
64K x 32 memory configuration
Supports high performance system speed
Commercial:
— 11 11ns Clock-to-Data Access (50 MHz)
Commercial and Industrial:
— 12 12ns Clock-to-Data Access (50 MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC64K32B2LG-XX)
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
IDT71V633
x
x
x
x
x
x
x
x
Description
The IDT71V633 is a 3.3V high-speed 2,097,152-bit (2-Mbit) SRAM
organized as 64K x 32 with full support of various processor interfaces
including the Pentium™ and PowerPC™. The flow-through burst archi-
tecture provides cost-effective 2-1-1-1 performance for processors up to
50 MHz.
The IDT71V633 SRAM contains write, data-input, address and control
registers. There are no registers in the data output path (flow-through
architecture). Internal logic allows the SRAM to generate a self-timed write
based upon a decision which can be left until the extreme end of the write
cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V633 can provide four cycles of data for
a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses will be
defined by the internal burst counter and the
LBO
input pin.
The IDT71V633 SRAM utilizes IDT's high-performance 3.3V CMOS
process, and is packaged in a JEDEC Standard 14mm x 20mm 100-pin
thin plastic quad flatpack (TQFP).
Pin Description
A
0
–A
15
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
–BW
4
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
–I/O
31
V
DD
, V
DDQ
V
SS
, V
SSQ
Address Inputs
Chip Enable
Chips Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock Input
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input/Output
Core and I/O Power Supply (3.3V)
Array Ground, I/O Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Power
Power
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
3780 tbl 01
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
AUGUST 2001
1
DSC-3780/05
©2000 Integrated Device Technology, Inc.
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
