IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Commercial And Industrial Temperature Ranges
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D
0
- D
17
)
Data inputs for 18-bit wide data.
OUTPUT ENABLE (
OE
)
When Output Enable (
OE
) is enabled (LOW), the parallel
output buffers receive data from the output register. When
OE
is disabled (HIGH), the Q output data bus is in a high-
impedance state.
LOAD (
LD
)
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
devices contain two 12-bit offset registers with data on the
inputs, or read on the outputs. When the Load (
LD
) pin is set
LOW and
WEN
is set LOW, data on the inputs D0-D11 is
written into the Empty offset register on the first LOW-to-HIGH
transition of the write clock (WCLK). When the
LD
pin and
(
WEN
) are held LOW then data is written into the Full offset
register on the second LOW-to-HIGH transition of the write
clock (WCLK). The third transition of the write clock (WCLK)
again writes to the Empty offset register.
However, writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then
by bringing the
LD
pin HIGH, the FIFO is returned to normal
read/write operation. When the LD pin is set LOW, and
WEN
is LOW, the next offset register in sequence is written.
CONTROLS:
RESET (
RS
)
Reset is accomplished whenever the Reset (
RS
) input is
taken to a LOW state. During reset, both internal read and
write pointers are set to the first location. A reset is required
after power-up before a write operation can take place. The
Full Flag (
FF
), Half-Full Flag (
HF
) and Programmable Almost-
Full Flag (
PAF
) will be reset to HIGH after t
RSF
. The Empty
Flag (
EF
) and Programmable Almost-Empty Flag (
PAE
) will be
reset to LOW after t
RSF
. During reset, the output register is
initialized to all zeros and the offset registers are initialized to
their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the
write clock (WCLK). Data set-up and hold times must be met with
respect to the LOW-to-HIGH transition of the write clock (WCLK).
The write and read clocks can be asynchronous or coincident.
WRITE ENABLE (
WEN
)
When the
WEN
input is LOW and
LD
input is HIGH, data
may be loaded into the FIFO RAM array on the rising edge of
every WCLK cycle if the device is not full. Data is stored in the
RAM array sequentially and independently of any ongoing
read operation.
When
WEN
is HIGH, no new data is written in the RAM
array on each WCLK cycle.
To prevent data overflow,
FF
will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle,
FF
will go HIGH allowing a write to occur. The
FF
flag is updated on
the rising edge of WCLK.
WEN
is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition
of the read clock (RCLK), when Output Enable (
OE
) is set LOW.
The write and read clocks can be asynchronous or coincident.
READ ENABLE (
REN
)
When Read Enable is LOW and
LD
input is HIGH, data is
loaded from the RAM array into the output register on the
rising edge of every RCLK cycle if the device is not empty.
When the
REN
input is HIGH, the output register holds the
previous data and no new data is loaded into the output
register. The data outputs Q
0
-Q
n
maintain the previous data
value.
Every word accessed at Q
n
, including the first word written
to an empty FIFO, must be requested using
REN
. When the
last word has been read from the FIFO, the Empty Flag (
EF
)
will go LOW, inhibiting further read operations.
REN
is ignored
when the FIFO is empty. Once a write is performed,
EF
will go
HIGH allowing a read to occur. The
EF
flag is updated on the
rising edge of RCLK.
LD
0
WEN
0
WCLK
Selection
Writing to offset registers:
Empty Offset
Full Offset
0
1
1
1
0
1
No Operation
Write Into FIFO
No Operation
NOTE:
2766 tbl 08
1. The same selection sequence applies to reading from the registers.
REN
is enabled and read is performed on the LOW-to-HIGH transition of
RCLK.
Figure 2. Write Offset Register
17
11
EMPTY OFFSET REGISTER
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
0
17
11
FULL OFFSET REGISTER
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
0
2766 drw 05
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
