CMOS SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
Integrated Device Technology, Inc.
IDT72255
IDT72265
FEATURES:
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8,192 x 18-bit storage capacity (IDT72255)
16,384 x 18-bit storage capacity (IDT72265)
10ns read/write cycle time (8ns access time)
Retransmit Capability
Auto power down reduces power consumption
Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings
Empty, Full and Half-full flags signal FIFO status
Programmable Almost Empty and Almost Full flags, each
flag can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or
First Word Fall Through timing (using
OR
and
IR
flags)
Easily expandable in depth and width
Independent read and write clocks (permit simultaneous
reading and writing with one clock signal)
Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-
pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)
Output enable puts data outputs into high impedance
High-performance submicron CMOS technology
Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72255/72265 are monolithic, CMOS, high capac-
ity, high speed, low power First-In, First-Out (FIFO) memories
with clocked read and write controls. These FIFOs are appli-
cable for a wide variety of data buffering needs, such as optical
disk controllers, local area networks (LANs), and inter-proces-
sor communication.
Both FIFOs have an 18-bit input port (D
n
) and an 18-bit
output port (Q
n
). The input port is controlled by a free-running
clock (WCLK) and a data input enable pin (
WEN
). Data is
written into the synchronous FIFO on every clock when
WEN
is asserted. The output port is controlled by another clock pin
(RCLK) and enable pin (
REN
). The read clock can be tied to
the write clock for single clock operation or the two clocks can
run asynchronously for dual clock operation. An output enable
pin (
OE
) is provided on the read port for three-state control of
the outputs.
The IDT72255/72265 have two modes of operation: In the
IDT Standard Mode
, the first word written to the FIFO is
deposited into the memory array. A read operation is required
to access that word. In the
First Word Fall Through Mode
(FWFT), the first word written to an empty FIFO appears
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D
0
-D
17
LD SEN
•
•
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
•
•
RAM ARRAY
8,192 x 18
16,384 x 18
FLAG
LOGIC
FF
/
IR
PAF
EF
/
OR
PAE
HF
FWFT/SI
WRITE POINTER
READ POINTER
•
•
READ
CONTROL
LOGIC
OUTPUT REGISTER
RT
MRS
PRS
FS
RESET
LOGIC
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•
•
RCLK
REN
TIMING
OE
Q
0
-Q
17
3037 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1997
Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3037/7
1
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
