VARIABLE WIDTH SUPERSYNC™ FIFO
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
Integrated Device Technology, Inc.
IDT72264
IDT72274
FEATURES:
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Select 8192 x 18 or 16384x 9 organization (IDT72264)
Select 16384 x 18 or 32678 x 9 organization (IDT72274)
Flexible control of read and write clock frequencies
Reduced dynamic power dissipation
Auto power down minimizes power consumption
15 ns read/write cycle time (10 ns access time)
Retransmit Capability
Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings
Empty, full and half-full flags signal FIFO status
Programmable almost empty and almost full flags, each
flag can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or
First Word Fall Through timing (using
OR
and
IR
flags)
Easily expandable in depth and width
Independent read and write clocks (permits simultaneous
reading and writing with one clock signal)
Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-
pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)
Output enable puts data outputs into high impedance
High-performance submicron CMOS technology
• Industrial temperature range (-40
O
C to +85
O
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72264/72274 are monolithic, CMOS, high capac-
ity, high speed, low power first-in, first-out (FIFO) memories
with clocked read and write controls. These FIFOs have three
main features that distinguish them among SuperSync FIFOs:
First, the data path width can be changed from 9-bits to 18-
bits; as a result, halving the depth. A pin called Memory Array
Select (MAC) chooses between the two options. This feature
helps reduce the need for redesigns or multiple versions of PC
cards, since a single layout can be used for both data bus
widths.
Second, IDT72264/72274 offer the greatest flexibility for
setting and varying the read and write clock (WCLK and
RCLK) frequencies. For example, given that the two clock
frequencies are unequal, the slower clock may exceed the
faster by, at most, twice its frequency. This feature is espe-
cially useful for communications and network applications
where clock frequencies are switched to permit different data
rates.
FUNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D
0
-D
n
LD SEN
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INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
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RAM ARRAY
8192 x 18 or 16384 x 9
16384 x 18 or 32768 x 9
FLAG
LOGIC
FF
/
IR
PAF
EF
/
OR
PAE
HF
FWFT/SI
WRITE POINTER
READ POINTER
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•
MAC
MEMORY ARRAY
CONFIGURATION
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
MRS
PRS
FS
RESET
LOGIC
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•
RCLK
REN
TIMING
OE
COMMERCIAL TEMPERATURE RANGES
©1997
Integrated Device Technology, Inc
Q
0
-Q
n
3218 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
MAY 1997
DSC-3218/2
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
1
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
