PARALLEL BIDIRECTIONAL FIFO
512 x 18 & 1024 x 18
Integrated Device Technology, Inc.
IDT72511
IDT72521
FEATURES:
• Two side-by-side FIFO memory arrays for bidirectional
data transfers
• 512 x 18-Bit - 512 x 18-Bit (IDT72511)
• 1024 x 18-Bit - 1024 x 18-Bit (IDT72521)
• 18-bit data buses on Port A side and Port B side
• Can be configured for 18-to-18-bit or 36-to-36-bit com-
munication
• Fast 35ns access time
• Fully programmable standard microprocessor interface
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Two programmable flags, Almost-Empty and Almost-Full
for each FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• Any of the eight flags can be assigned to four external
flag pins
• Flexible reread/rewrite capabilities
• Six general-purpose programmable I/O pins
• Standard DMA control pins for data exchange with
peripherals
• 68-pin PGA and PLCC packages
DESCRIPTION:
The IDT72511 and IDT72521 are highly integrated first-in,
first-out memories that enhance processor-to-processor and
processor-to-peripheral communications. IDT BiFIFOs inte-
grate two side-by-side memory arrays for data transfers in
two directions.
The BiFIFOs have two ports, A and B, that both have
standard microprocessor interfaces. All BiFIFO operations
are controlled from the 18-bit wide Port A. Port B is also 18
bits wide and can be connected to another processor or a
peripheral controller. The BiFIFOs have a 9-bit bypass path
that allows the device connected to Port A to pass messages
directly to the Port B device.
Ten registers are accessible through Port A, a Com-
mand Register, a Status Register, and eight Configuration
Registers.
The IDT BiFIFO has programmable flags. Each FIFO
memory array has four internal flags, Empty, Almost-Empty,
Almost-Full and Full, for a total of eight internal flags. The
Almost-Empty and Almost-Full flag offsets can be set to any
depth through the Configuration Registers. These eight inter-
nal flags can be assigned to any of four external flag pins
(FLG
A
-FLG
D
) through one Configuration Register.
Port B has programmable I/O, reread/rewrite and DMA
functions. Six programmable I/O pins are manipulated through
SIMPLIFIED BLOCK DIAGRAM
18-Bit
FIFO
18-bits
Data
Bypass
9-bits
18-bits
Data
Port
A
18-Bit
FIFO
Port
B
Programmable
I/O Logic
I/O
Control
Processor
Interface
A
Programmable
Flag Logic
Registers
Processor
Interface
B
Handshake
Interface
Control
Flags
DMA
2668 drw 01
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
DECEMBER 1995
DSC-2668/6
5.32
1
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
