IDT72605/IDT72615 CMOS SyncBiFIFO
256 x 18 x 2 and 512 x 18 x 2
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 2
2704 tbl 07
+5V
1.1KΩ
D.U.T.
680Ω
30pF*
2704 drw 05
AC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 5V±10%, T
A
= 0°C to +70°C)
72615L20
72605L20
Min.
Max.
—
50
20
8
8
20
12
12
—
3
6
1
6
1
3
0
3
—
—
—
—
10
17
—
—
—
—
—
—
27
10
—
—
—
—
10
—
10
10
10
12
12
—
—
or equivalent circuit
Figure 2. Output Load
* Includes jig and scope capacitances.
Symbol
f
CLK
t
CLK
t
CLKH
t
CLKL
t
RS
t
RSS
t
RSR
t
RSF
t
A
t
CS
t
CH
t
DS
t
DH
t
OE
t
OLZ
t
OHZ
t
FF
t
EF
t
PAE
t
PAF
t
SKEW1
t
SKEW2
Parameter
Clock frequency
Clock cycle time
Clock HIGH time
Clock LOW time
Reset pulse width
Reset set-up time
Reset recovery time
Reset to flags in intial state
Data access time
Control signal set-up time
(1)
Control signal hold time
(1)
Data set-up time
Data hold time
Output Enable LOW to
output data valid
(2)
Output Enable LOW to data
bus at Low-Z
(2)
Output Enable HIGH to data
bus at High-Z
(2)
Clock to Full Flag time
Clock to Empty Flag time
Clock to Programmable
Almost Empty Flag time
Clock to Programmable
Almost Full Flag time
Skew between CLK
A
& CLK
B
for Empty/Full Flags
(2)
Skew between CLK
A
& CLK
B
for Programmable Flags
(2)
Commercial
72615L25
72615L35
72615L50
72605L25
72605L35
72605L50
Min. Max. Min. Max. Min.
Max. Unit
—
40
—
28
—
20 MHz
25
10
10
25
15
15
—
3
6
1
6
1
3
0
3
—
—
—
—
12
19
—
—
—
—
—
—
28
15
—
—
—
—
13
—
13
15
15
15
15
—
—
35
14
14
35
21
21
—
3
8
1
8
1
3
0
3
—
—
—
—
17
25
—
—
—
—
—
—
35
21
—
—
—
—
20
—
20
21
21
21
21
—
—
50
20
20
50
30
30
—
3
10
1
10
1
3
0
3
—
—
—
—
20
34
—
—
—
—
—
—
50
25
—
—
—
—
28
—
28
30
30
30
30
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing Figures
—
4,5,6,7
4,5,6,7,12,13,14,15
4,5,6,7,12,13,14,15
3
3
3
3
5,7,8,9,10,11
4,5,6,7,8,9,10,11,
12, 13,14,15
4,5,6,7,10,11,12,
13, 14,15
4,6,8,9,10,11
4,6
5,7,8,9,10,11
5,7,8,9,10,11
5,7,10,11
4,6,10,11
5,7,8,9,10,11
12,14
13,15
4,5,6,7,8,9,10,11
4, 7,12,13,14,15
NOTES:
1. Control signals refer to
CS
A
, R/
W
A
,
EN
A
, A
2
, A
1
, A
0
, R/
W
B
,
EN
B
.
2. Minimum values are guaranteed by design.
2704 tbl 08
5.18
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
