IDT72801/728211/72821/72831/72841/72851
Commercial And Industrial Temperature Range
When either of the two Read Enable
RENA1, RENA2
(RENB1,
RENB2)
associated with FIFO A (B) is HIGH, the output register holds the previous data
and no new data is allowed to be loaded into the register.
When all the data has been read from FIFO A (B), the Empty Flag
EFA
(EFB)
will go LOW, inhibiting further read operations. Once a valid write operation has
been accomplished,
EFA
(EFB) will go HIGH after tREF and a valid read can
begin. The Read Enables
RENA1, RENA2
(RENB1,
RENB2)
are ignored when
FIFO A (B) is empty.
Output Enable (OEA,
OEB)
— When Output Enable
OEA
(OEB) is enabled
(LOW), the parallel output buffers of FIFO A (B) receive data from their respective
output register. When Output Enable
OEA
(OEB) is disabled (HIGH), the QA
(QB) output data bus is in a high-impedance state.
Write Enable 2/Load (WENA2/LDA,
WENB2/LDB)
— This is a dual-
purpose pin. FIFO A (B) is configured at Reset to have programmable flags
or to have two write enables, which allows depth expansion. If WENA2/LDA
(WENB2/LDB) is set HIGH at Reset
RSA
= LOW (RSB = LOW), this pin operates
as a second write enable pin.
If FIFO A (B) is configured to have two write enables, when Write Enable
1
WENA1
(WENB1) is LOW and WENA2/LDA (WENB2/LDB) is HIGH, data can be
loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock WCLKA (WCLKB). Data is stored in the array sequentially
and independently of any ongoing read operation.
In this configuration, when
WENA1
(WENB1) is HIGH and/or WENA2/LDA
(WENB2/LDB) is LOW, the input register of Array A holds the previous data and
no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag
FFA
(FFB) will go LOW, inhibiting
further write operations. Upon the completion of a valid read cycle,
FFA
(FFB)
will go HIGH after tWFF, allowing a valid write to begin.
WENA1,
(WENB1) and
WENA2/LDA (WENB2/LDB) are ignored when the FIFO is full.
FIFO A (B) is configured to have programmable flags when the WENA2/
LDA
(WENB2/LDB) is set LOW at Reset
RSA
= LOW (RSB = LOW). Each FIFO
contains four 8-bit offset registers which can be loaded with data on the inputs,
or read on the outputs. See Figure 3 for details of the size of the registers and
the default values.
If FIFO A (B) is configured to have programmable flags, when the
WENA1
(WENB1) and WENA2/LDA (WENB2/LDB) are set LOW, data on the DA (DB)
inputs are written into the Empty (Least Significant Bit) Offset register on the first
LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the
Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH
transition of WCLKA (WCLKB), into the Full (Least Significant Bit) Offset register
on the third transition, and into the Full (Most Significant Bit) Offset register on
the fourth transition. The fifth transition of WCLKA (WCLKB) again writes to the
Empty (Least Significant Bit) Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing
LDA
(LDB) HIGH, FIFO
A (B) is returned to normal read/write operation. When
LDA
(LDB) is set LOW,
and
WENA1
(WENB1) is LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the QA (QB) outputs when
WENA2/LDA (WENB2/LDB) is set LOW and both Read Enables
RENA1, RENA2
(RENB1,
RENB2)
are set LOW. Data can be read on the LOW-to-HIGH transition
of the Read Clock RCLKA (RCLKB).
SIGNAL DESCRIPTIONS
FIFO A and FIFO B are identical in every respect. The following description
explains the interaction of input and output signals for FIFO A. The correspond-
ing signal names for FIFO B are provided in parentheses.
INPUTS:
Data In (DA0 – DA8, DB0 – DB8)
—
DA0 - DA8 are the nine data inputs
for memory array A. DB0 - DB8 are the nine data inputs for memory array B.
CONTROLS:
Reset
(
RSA, RSB)
— Reset of FIFO A (B) is accomplished whenever
RSA
(RSB) input is taken to a LOW state. During Reset, the internal read and write
pointers associated with the FIFO are set to the first location. A Reset is required
after power-up before a write operation can take place. The Full Flag
FFA
(FFB)
and Programmable Almost-Full flag
PAFA
(PAFB) will be reset to HIGH after
tRSF. The Empty Flag
EFA
(EFB) and Programmable Almost-Empty flag
PAEA
(PAEB) will be reset to LOW after tRSF. During Reset, the output register is
initialized to all zeros and the offset registers are initialized to their default values.
Write Clock (WCLKA, WCLKB)
— A write cycle to Array A (B) is
initiated on the LOW-to-HIGH transition of WCLKA (WCLKB). Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of
WCLKA (WCLKB). The Full Flag
FFA
(FFB) and Programmable Almost-Full
flag
PAFA
(PAFB) are synchronized with respect to the LOW-to-HIGH transition
of the Write Clock WCLKA (WCLKB).
The Write and Read Clocks can be asynchronous or coincident.
Write Enable 1
(WENA1,
WENB1)
— If FIFO A (B) is configured for
programmable flags,
WENA1
(WENB1) is the only enable control pin. In this
configuration, when
WENA1
(WENB1) is LOW, data can be loaded into the input
register of RAM Array A (B) on the LOW-to-HIGH transition of every Write Clock
WCLKA (WCLKB). Data is stored in Array A (B) sequentially and independently
of any ongoing read operation.
In this configuration, when
WENA1
(WENB1) is HIGH, the input register holds
the previous data and no new data is allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which allows for depth
expansion. See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow,
FFA
(FFB) will go LOW, inhibiting further write
operations. Upon the completion of a valid read cycle, the
FFA
(FFB) will go HIGH
after t
WFF
, allowing a valid write to begin.
WENA1
(WENB1) is ignored when FIFO
A (B) is full.
Read Clock (RCLKA, RCLKB)
— Data can be read from Array A (B) on
the LOW-to-HIGH transition of RCLKA (RCLKB). The Empty Flag
EFA
(EFB)
and Programmable Almost-Empty Flag
PAEA
(PAEB) are synchronized with
respect to the LOW-to-HIGH transition of RCLKA (RCLKB).
The Write and Read Clocks can be asynchronous or coincident.
Read Enables (RENA1,
RENA2, RENB1, RENB2)
— When both Read
Enables
RENA1, RENA2
(RENB1,
RENB2)
are LOW, data is read from Array
A (B) to the output register on the LOW-to-HIGH transition of the Read Clock
RCLKA (RCLKB).
6
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