IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFOTM 131,072 x 18, 262,144 x 18
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed.Areadoperation,whichconsists ofactivatingRENandenabling
a rising RCLK edge, will shift the word from internal memory to the data
output lines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequentwords writtentothe FIFOdorequire a LOWonREN foraccess.
The state of the FWFT/SI input during Master Reset determines the timing
mode in use.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and
FF functions are selected in IDT Standard mode. The IR and OR functions
are selectedinFWFTmode. HF, PAE andPAF arealways availableforuse,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point
in memory. (See Table I and Table II.) Programmable offsets determine
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that PAE can be set
to switch at 127 or 1,023 locations from the empty boundary and the PAF
thresholdcanbesetat127or1,023locations fromthefullboundary. These
choices are made with the LD pin during Master Reset.
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming, WEN together with LD on each rising edge of WCLK,
are used to load the offset registers via Dn. REN together with LD on each
rising edge of RCLK can be used to read the offsets in parallel from Qn
regardless of whether serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: The read and
write pointers are settothe firstlocationofthe FIFO. The FWFTpinselects
IDT Standard mode or FWFT mode. The LD pin selects either a partial flag
default setting of 127 with parallel programming or a partial flag default
setting of 1,023 with serial programming. The flags are updated according
to the timing mode and default offsets selected.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timingmodeandoffsets ineffect. PRSis usefulforresettingadeviceinmid-
operation, when reprogramming partial flags would be undesirable.
The Retransmitfunctionallows data tobe rereadfromthe FIFO. ALOW
on the RT input during a rising RCLK edge initiates a retransmit operation
by setting the read pointer to the first location of the memory array.
If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by
activating control inputs) will immediately take the device out of the power
down state.
The IDT72V295/72V2105 are fabricated using IDT’s high speed submi-
cron CMOS technology.
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE ENABLE (WEN)
LOAD (LD)
DATA IN (D
0
- Dn)
DATA OUT (Q0 - Qn)
IDT
72V295
72V2105
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF FULL FLAG (HF)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
4668 drw 03
Figure 1. Block Diagram of Single 131,072 x 18 and 262,144 x 18 Synchronous FIFO
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