IDT72V90823 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
SYMBOL
IM
(1)
AD0-7
(1)
D8-15
(1)
DTA
(1)
NAME
CPU Interface Mode
Address/Data Bus
0 to 7
Data Bus 8-15
Data Transfer
Acknowledgment
Control Output
Output Drive Enable
I/O
I
I/O
I/O
O
DESCRIPTION
When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor
port is in non-multiplexed mode.
These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins
are also the input address bits of the microprocessor port.
These pins are the eight most significant data bits of the microprocessor port.
This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin
drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A
pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1,024 or 2.048 bits per frame respectively. The
level of each bit is determined by the CCO bit in the connection memory. See External Drive Control Section.
This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB
bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per channel control bit in the connection memory.
CCO
(1)
ODE
(1)
O
I
NOTE:
1. These pins are 5V tolerant.
5
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
