FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET
Integrated Device Technology, Inc.
IDT54/74FCT273T/AT/CT
FEATURES:
•
•
•
•
Std., A, and C speed grades
Low input and output leakage
≤1µA
(max.)
CMOS power levels
True TTL input and output compatibility
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Product available in Radiation Tolerant and Radiation
Enhanced versions
Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
DESCRIPTION:
The IDT54/74FCT273T/AT/CT are octal D flip-flops built
using an advanced dual metal CMOS technology. The IDT54/
74FCT273T/AT/CT have eight edge-triggered D-type flip-
flops with individual D inputs and O outputs. The common
buffered Clock (CP) and Master Reset ( ) inputs load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s O
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the
input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
MR
•
•
•
•
•
MR
FUNCTIONAL BLOCK DIAGRAM
D
0
CP
D
CP
R
D
MR
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
2568 drw 03
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
PIN CONFIGURATIONS
D
0
3
D
1
O
1
O
2
D
2
D
3
4
5
6
7
8
9 10 11 12 13
2568 drw 01
MR
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
2
3
4
5
6
7
8
9
10
19
P20-1
D20-1
SO20-2
SO20-8
&
E20-1
18
17
16
15
14
13
12
11
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
2
1
20 19
18
17
L20-2
16
15
14
D
7
D
6
O
6
O
5
D
5
O
0
1
20
V
CC
O
3
GND
CP
O
4
D
4
MR
V
CC
O
7
INDEX
2568 drw 02
DIP/SOIC/QSOP/CERPACK
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
LCC
TOP VIEW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995
Integrated Device Technology, Inc.
APRIL 1995
DSC-4209/3
6.10
1
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
