QUAD 2:1 MUX/DEMUX
BUS SWITCH
Integrated Device Technology, Inc.
IDT74FST3257
PRELIMINARY
FEATURES:
• Bus switches provide zero delay paths
• Extended commercial range of –40°C to +85°C
• Low switch on-resistance:
FST3xxx – 5Ω
• TTL-compatible input and output levels
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in QSOP and SOIC
DESCRIPTION:
The FST3257 belongs to IDT's family of Bus switches. Bus
switch devices perform the function of connecting or isolating
two ports without providing any inherent current sink or source
capability. Thus they generate little or no noise of their own
while providing a low resistance path for an external driver.
These devices connect input and output ports through an n-
channel FET. When the gate-to-source junction of this FET is
adequately forward-biased the device conducts or the resis-
tance between input and output ports is small. Without
adequate bias on the gate-to-source junction of the FET, the
FET is turned off, therefore with no V
CC
applied, the device
has hot insertion capability.
The low on-resistance and simplicity of the connection
between input and output ports reduces the delay in this path
to close to zero.
The FST3257 provides a 4-bit 2:1 multiplexer/demultiplexer.
The S pin controls the mux select and the
E
pin serves as the
switch enable.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
I
0A
Z
A
I
1A
I
0B-D
Z
B-D
I
1B-D
3 Channels
S
S
I
0A
I
1A
Z
A
I
0B
I
1B
Z
B
GND
1
2
3
4
5
6
7
8
SOIC/QSOP
TOP VIEW
16
15
14
SO16-1
SO16-7
13
12
11
10
9
Vcc
E
I
0C
I
1C
Z
C
1
0D
I
1D
Z
D
E
3257 drw 01
3257 drw 02
PIN DESCRIPTION
Pin Names
I
0A-
I
0D
I
1A-
I
1D
I/O
I/O
I/O
I
I
I/O
Description
Port 0
Port 1
Switch Enable (Active Low)
Mux Select
Port Z
3257 tbl 01
E
S
Z
A-
Z
B
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
©1996
Integrated Device Technology, Inc.
AUGUST 1996
10.3
DSC-3257/3
1
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
