IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO 24-BIT
MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
IDT74ALVCH16260
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual
metal CMOS technology. The ALVCH16260 is used in applications in which
two separate data paths must be multiplexed onto, or demultiplexed from, a
single data path. Typical applications include multiplexing and/or demultiplexing
address and data information in microprocessor or bus-interface applications.
This device also is useful in memory interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available
for address and/or data transfer. The output-enable (OE1B,
OE2B,
and
OEA)
inputs control the bus transceiver functions. The
OE1B
and
OE2B
control
signals also allow bank control in the A-to-B direction. Address and/or data
information can be stored using the internal storage latches. The latch-enable
(LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage.
When the latch-enable input is high, the latch is transparent. When the latch-
enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The ALVCH16260 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16260 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OE1B
LEA1B
29
30
A-1B
LATCH
12
1
B
1:12
LE1B
SEL
OEA
2
12
28
1
1B-A
LATCH
12
12
A
1:12
12
M
U
X
1
0
12
12
LE2B
27
2B-A
LATCH
12
LEA2B
O E2B
55
A-2B
LATCH
2
B
1:12
12
56
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4737/2
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
