IDT74ALVCH16373
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
TRANSPARENT D-TYPE
LATCH WITH 3-STATE
OUTPUTS AND BUS-HOLD
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• V
CC
= 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
IDT74ALVCH16373
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
This 16-bit transparent D-type latch is built using advanced dual metal CMOS
technology. The ALVCH16373 is particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and working registers. This device
can be used as two 8-bit latches or one 16-bit latch. When the latch enable (LE)
input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the
Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) can be used to place the eight outputs in either
a normal logic state (high or low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load nor drive the bus lines signifi-
cantly. The high-impedance state and the increased drive provide the capability
to drive bus lines without need for interface or pullup components.
OE
does not
affect internal operations of the latch. Old data can be retained or new data can
be enetered while the outputs are in the high-impedance state.
The ALVCH16373 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16373 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistor.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
2
OE
24
1
LE
48
2
LE
25
C1
2
C1
1
Q
1
2
D
1
36
13
2
Q
1
1
D
1
47
1D
1D
TO 7 OTHER CHAN NELS
TO 7 OTHER CHAN NELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4574/2
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
