155 Mbps ATM SAR Controller
With ABR Support for PCI-based
Networking Applications
IDT77252
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Full-duplex Segmentation and Reassembly (SAR) at 155
Mbps "wire-speed" (310 Mbps aggregate speed)
Operates with ATM Networks up to 155.52 Mbps
Stand-alone Controller: Embedded Processor not required
Performs ATM Layer Protocol Functions
Supports AAL5, AAL3/4, AAL0 and Raw Cell Formats
Supports Constant Bit Rate (CBR), Variable Bit Rate (VBR),
and Unassigned Bit Rate (UBR), and Available Bit Rate
(ABR) Service Classes
Segments and Reassembles CS-PDUs into Host Memory
Up to 16K Open Transmit Connections
Up to 16K Simultaneous Receive Connections
ABR, VBR, UBR Selectable per VC Time-out
Automatic AAL5 Padding
Four Buffer Pools for Independent or Chained Reassembly
Supports Any Buffer Alignment Condition
Free Buffer Queues Mapped Into PCI Memory Space
Rx FIFO Size (Configurable to 1024 Kbytes)
Configurable Transmit FIFO Depth for Reduced Latency
Supports Big and Little Endian Data Transfers
Null Cell Disable Option During Transmit
NAND Test Mode
RM Cell Handling
UTOPIA Level 1 Interface to PHY
Utility Bus Interface for PHY Management
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Serial EEPROM Interface
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EPROM Interface
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PCI 2.1 Compliant
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UNI 3.1, TM 4.0 Compliant
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Meets PCI Bus Power Management and Interface
Specification Revision 1.1
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Pin Compatible with IDT 77211 SAR
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Commercial and Industrial Temperature Ranges
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208-Lead PQFP Package (28 x 28mm)
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Software Drivers:
– SARWIN 2 Demonstration Program
– NDIS Driver
– Vx Works (3rd party)
– Linux (3rd party)
The IDT77252 NICStAR
™
is a member of IDT's family of products for
Asynchronous Transfer Mode (ATM) networks. The ABR SAR performs
both the ATM Adaptation Layer (AAL) Segmentation and Reassembly
(SAR) function and the ATM layer protocol functions.
A Network Interface Card (NIC) or internetworking product based on
the ABR SAR uses host memory, rather than local memory, to reas-
semble Convergence Sublayer Protocol Data Units (CS-PDUs) from
ATM cell payloads received from the network. When transmitting, as CS-
PDUs become ready, they are queued in host memory and segmented
16K x 32 to 512K x 32
SRAM
PCI BUS
8
EPROM
32
Rx UTOPIA Bus
PCI Interface
8
33MHZ
32
IDT77252
155Mbps
PCI ATM
ABR SAR
155Mbps
PHY
2
2
Tx UTOPIA Bus
8
Utility Bus
8
80.0MHZ OSC.
EEPROM
4057 drw 01
1 of 17
2001 Integrated Device Technology, Inc.
March 26, 2001
DSC 4057/8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
