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MPC905 参数 Datasheet PDF下载

MPC905图片预览
型号: MPC905
PDF下载: 下载PDF文件 查看货源
内容描述: 1 : 6个PCI时钟发生器/扇出缓冲器 [1:6 PCI Clock Generator/Fanout Buffer]
分类和应用: 时钟发生器PC
文件页数/大小: 7 页 / 381 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC905/D
DATA SHEET
1:6 PCI Clock Generator/Fanout
1:6 PCI Clock Generator/
Buffer
Fanout Buffer
The MPC905 is a six output clock generation device targeted to
provide the clocks required in a 3.3V or 5.0V PCI environment. The
device operates from a 3.3V supply and can interface to either a TTL
input or an external crystal. The inputs to the device can be driven with
5.0V when the VCC is at 3.3V. The outputs of the MPC905 meet all of the
specifications of the PCI standard.
MPC905
MPC905
Freescale Semiconductor, Inc...
Six Low Skew Outputs
Synchronous Output Enables for Power Management
Low Voltage Operation
XTAL Oscillator Interface
16-Lead SOIC Package
5.0V Tolerant Enable Inputs
1:6 PCI
CLOCK GENERATOR/
FANOUT BUFFER
The MPC905 device is targeted for PCI bus or processor bus
environments with up to 12 clock loads. Each of the six outputs on the
16
1
MPC905 can drive two series terminated 50Ω transmission lines. This
capability effectively makes the MPC905 a 1:12 fanout buffer.
D SUFFIX
The MPC905 offers two synchronous enable inputs to allow users
PLASTIC SOIC PACKAGE
flexibility in developing power management features for their designs.
CASE 751B-05
Both enable signals are active HIGH inputs. A logic ‘0’ on the Enable1 will
pull outputs 0 to 4 into the logic ‘0’ state. A logic ‘1’ on the Enable1 input
will result in outputs 0 to 4 to be toggling. A logic ‘0’ on Enable2 will cause
output BLK5 to a logic ‘0’ state, whereas a logic ‘1’ on Enable2 will cause
output BLK5 to toggle. The oscillator remains on.
The Enable2 input can be used to disable any high power device for system power savings during periods of inactivity. Both
enable inputs are synchronized internal to the chip so that the output disabling will happen only when the outputs are already
LOW. This feature guarantees no runt pulses will be generated during enabling and disabling.
VDD (3)
GND (3)
Pinout: 16-Lead Plastic Package
(Top View)
BCLK0
XTAL_OUT 1
XTAL_IN
BCLK1
BCLK2
XTAL_OUT
BCLK3
BCLK4
SYNCHRONIZE
BCLK5
Enable2
SYNCHRONIZE
Enable2 2
GND1 3
BCLK0 4
VDD1 5
Enable1
BCLK1 6
GND2 7
BCLK2 8
16 XTAL_IN
15 Enable1
14 BCLK5
13 VDD3
12 BCLK4
11 GND3
10 BCLK3
9 VDD2
For More Information On This Product,
REV 2
1
Go to: www.freescale.com
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
IDT™
1:6 PCI Clock Generator/Fanout Buffer
01/01
©
Motorola, Inc. 2001
MPC905
1