欢迎访问ic37.com |
会员登录 免费注册
发布采购

IN74HCT373ADW 参数 Datasheet PDF下载

IN74HCT373ADW图片预览
型号: IN74HCT373ADW
PDF下载: 下载PDF文件 查看货源
内容描述: 八路三态同相透明锁存器 [Octal 3-State Noninverting Transparent Latch]
分类和应用: 锁存器
文件页数/大小: 6 页 / 310 K
品牌: IKSEMICON [ IK SEMICON CO., LTD ]
 浏览型号IN74HCT373ADW的Datasheet PDF文件第1页浏览型号IN74HCT373ADW的Datasheet PDF文件第2页浏览型号IN74HCT373ADW的Datasheet PDF文件第3页浏览型号IN74HCT373ADW的Datasheet PDF文件第5页浏览型号IN74HCT373ADW的Datasheet PDF文件第6页  
IN74HCT373A
AC ELECTRICAL CHARACTERISTICS
(V
CC
=5.0 V
±
10%, C
L
=50pF, t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C
to
-55°C
28
32
30
35
12
10
15
≤85°C
≤125°C
Unit
t
PLH
, t
PHL
t
PLH
, t
PHL
t
PLZ
, t
PHZ
t
PZL
, t
PZH
t
TLH
, t
THL
C
IN
C
OUT
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
Maximum Propagation Delay , Latch Enable to Q
(Figures 2 and 5)
Maximum Propagation Delay ,Output Enable to
Q (Figures 3 and 6)
Maximum Propagation Delay , Output Enable to
Q (Figures 3 and 6)
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Latch)
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
Minimum Hold Time,Latch Enable to Input D
(Figure 4)
Minimum Pulse Width, Latch Enable (Figure 2)
Maximum Input Rise and Fall Times (Figure 1)
35
40
38
44
15
10
15
42
48
45
53
18
10
15
ns
ns
ns
ns
ns
pF
pF
T
A
=25°C,V
CC
=5.0 V
65
pF
C
PD
t
SU
t
h
t
w
t
r,
t
f
10
10
12
500
13
13
15
500
15
15
18
500
ns
ns
ns
ns
Rev. 00