TECHNICAL DATA
Phase Comparator 2
This detector is a digital memory network. It
consists of four flip-flops and some gating logic, a three
state output and a phase pulse output as shown in Figure 6.
This comparator acts only on the positive edges of the
input signals and is independent of duty cycle.
Phase comparator 2 operates in such a way as to
force the PLL into lock with 0 phase difference between
the VCO output and the signal input positive waveform
edges. Figure 8 shows some typical loop waveforms. First
assume that SIG
IN
is leading the COMP
IN
. This means that
the VCO’s frequency must be increased to bring its leding
edge into proper phase alignment. Thus the phase detector
2 output is set high. This will cause the loop filter to
charge up the VCO input, increasing the VCO frequency.
Once the leading edge of the COMP
IN
is detected, the
output goes TRI-STATE holding the VCO input at the
loop filter voltage. If the VCO still lags the SIG
IN
then the
phase detector will again charge up the VCO input for the
time between the leading edges of both waveforms.
If the VCO leads the SIG
IN
then when the leading
edge of the VCO is seen; the output of the phase
comparator goes low. This discharges the loop filter until
the leading edge of the SIG
IN
is detected at which time the
output disables itself again. This has the effect of slowing
down the VCO to again make the rising edges of both
waveforms coincidental.
When the PLL is out of lock, the VCO will be
running either slower or faster than the SIG
IN
. If it is
running slower the phase detector will see more SIG
IN
rising edges and so the output of the phase comparator
will be high a majority of the time, raising the VCO’s
frequency. Conversely, if the VCO is running faster than
the SIG
IN
, the output of the detector will be low most of
the time and the VCO’s output frequency will be
decreased.
As one can see, when the PLL is locked, the output
of phase comparator 2 will be disabled except for minor
corrections at the leading edge of the waveforms. When
PC
2
is TRI-STATED, the PCP output is high. This output
can be used to determine when the PLL is in the locked
condition.
This detector has several interesting characteristics.
Over the entire VCO frequency range there is no phase
difference between the COMP
IN
and the SIG
IN
. The lock
range of the PLL is the same as the capture range.
Minimal power was consumed in the loop filter since in
lock the detector output is a high impedance. When no
SIG
IN
is present, the detector will see only VCO leading
edges, so the comparator output will stay low, forcing the
VCO to f
min
.
Phase comparator 2 is more susceptible to noise,
causing the PLL to unlock. If a noise pulse is seen on the
SIG
IN
, the comparator treats it as another positive edge of
the SIG
IN
and will cause the output to go high until the
VCO leding edge is see, potentially for an entire SIG
IN
period. This would cause the VCO to speed up during that
time. When using PC
1
, the output of that phase detector
would be disturbed for only the short duration of the noise
spike and would cause less upset.
Phase Comparator 3
This is positive edge-triggered sequential phase
detector using an RS flip-flop as shown in Figure 6. When
the PLL is using this comparator, the loop is controlled by
positive signal transitions and the duty factors of SIG
IN
and COMP
IN
are not important. It has some similar
characteristics to the edge sensitive comparator. To see
how this detector works, assume input pulses are applied
to the SIGN
IN
and COMP
IN
’s as shown in Figure 9. When
the SIGN
IN
leads the COMP
IN
, the flop is set. This will
charge the loop filter and cause the VCO to speed up,
bringing the comparator into phase with the SIG
IN
. The
phase angle between SIG
IN
and COMP
IN
varies from 0° to
360° and is 180° at f
o
. The voltage swing for PC
3
is
greater than for PC
2
but consequently has more ripple in
the signal to the VCO .When no SIG
IN
is present the VCO
will be forced to f
max
as opposed to fmin when PC
2
is used.
The operating characteristics of all three phase
comparators tors should be compared to the requirement
of the system design and the appropriate one should be
used.
Figure 8. Typical Waveforms for PLL Using
Phase Comparator 2
Figure 9. Typical Waveforms for PLL Using
Phase Comparator 3
9
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