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IW4052BN 参数 Datasheet PDF下载

IW4052BN图片预览
型号: IW4052BN
PDF下载: 下载PDF文件 查看货源
内容描述: 模拟多路复用器多路解复用器高性能硅栅CMOS [Analog Multiplexer Demultiplexer High-Performance Silicon-Gate CMOS]
分类和应用: 解复用器
文件页数/大小: 7 页 / 269 K
品牌: IKSEMICON [ IK SEMICON CO., LTD ]
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TECHNICAL DATA
IW4052B
Analog Multiplexer Demultiplexer
High-Performance Silicon-Gate CMOS
The IW4052B analog multiplexer/demultiplexer is digitally controlled
analog switches having low ON impedance and very low OFF leakage
current. Control of analog signals up to 20V peak-to-peak can be
achieved by digital signal amplitudes of 4.5 to 20V (if V
CC
- GND = 3V,
a V
CC
- V
EE
of up to 13 V can be controlled; for V
CC
- V
EE
level
differences above 13V a V
CC
- GND of at least 4.5V is required).
These multiplexer circuits dissipate extremely low quiescent power
over the full V
CC
-GND and V
CC
- V
EE
supply-voltage ranges,
independent of the logic state of the control signals. When a logic “1”is
present at the ENABLE input terminal all channels are off.
The IW4052 is a differential 4-channel multiplexer having two binary
control inputs. A and B, and an enable input. The two binary input signals
select 1 of 4 pairs of channels to turned on and connect the analog inputs
to the outputs.
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1μA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
N SUFFIX
PLASTIC
16
1
16
1
D SUFFIX
SOIC
ORDERING INFORMATION
IW4052BN
Plastic DIP
IW4052BD
SOIC
T
A
= -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
Double-Pole, 4-Position
Plus Common Off
FUNCTION TABLE
Control Inputs
Enable
B
L
L
L
L
PIN 16 =V
CC
PIN 7 = V
EE
PIN 8 = GND
L
L
H
H
Select
A
L
H
L
H
X
Y0
Y1
Y2
Y3
X0
X1
X2
X3
None
ON
Channels
H
X
H = high level
L = low level
X = don’t care
Rev. 00