Ei16C450
UART
Semiconductor, Inc.
FEATURES
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5V Operation
Full duplex asynchronous receiver and
transmitter
Easily interfaces to most popular
microprocessors
Adds or deletes standard asynchronous com-
munication bits (start, stop, and parity ) to or
from a serial data stream
Independently controlled transmitter, receiver,
line status, and data set interrupts
Programmable baud rate generator allows
division of any input clock by 1 to (2
16
-1) and
generates the internal 16 x clock
Independent receiver clock input
MODEM control functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Fully programmable serial interface characteris
tics:
- 5, 6, 7, or 8 bit characters
- Even, odd, or no-parity bit generation and
detection
- 1, 1.5, or 2 stop bit generation
- Baud generation (DC to 56k baud)
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False start bit detection
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Complete status reporting capabilities
Tri-State® TTL drive capabilities for bi-direc
tional data bus and control bus
Line break generation and detection
Internal diagnostic capabilities:
- Loopback controls for communications link fault
isolation
- Break, parity overrun, and framing error simulation
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Fully prioritized interrupt systems controls
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DESCRIPTION
The Epic Ei16C450 Universal Asynchronous Receiver
Transmitter (UART) is a CMOS-VLSI communication
device in a single package.
The UART performs serial to parallel conversion
on data characters received from a peripheral
device or a MODEM, and parallel-to-serial
conversions on data characters received from the
CPU. The CPU can read the complete status of the
UART at any time during the functional operation.
Status information reported includes the type and con-
dition of the transfer operation being performed by the
UART, as well as any error conditions (parity, overrun,
framing, or break detect).
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Part Numbers May Be Marked With "IMP" or "Ei."
PIN CONFIGURATION
DCD
•
DSR
•
CTS
•
38
VCC
N.C.
CSOUT
IOW
•
IOW
•
GND
IOR
•
N.C.
DDIS
•
XTAL1
40-PIN DIP
44-PIN PLCC
48-PIN TQFP
5
XTAL2
AS
•
N.C.
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2•
BAUDOUT•
XTAL1
XTAL2
DOSTR•
DOSTR
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
E
i
1
6
C
4
5
0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
RI•
DCD•
DSR•
CTS•
MR
OUT1•
DTR•
RTS•
OUT2•
INTRPT
NC
A0
A1
A2
ADS•
CSOUT
DDIS
DISTR
DISTR•
48
47
46
45
44
43
42
41
40
39
D4
D3
D2
D1
D0
NC
VCC
RI•
DCD•
CDSR•
CTS•
37
36
35
34
33
32
N.C.
D4
D3
D2
D1
D0
RI
N.C.
D5
1
2
3
4
5
6
7
8
9
10
11
12
16
17
19
22
20
21
13
14
15
18
23
24
N.C.
RESET
OP1
•
DTR
•
RTS
•
OP2
•
INT
N.C.
A0
A1
A2
N.C.
6
5
4
3
2
1
44
43
42
41
40
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2•
BAUDOUT•
7
8
9
10
11
12
13
14
15
16
17
Ei16C450
39
38
37
36
35
34
33
32
31
30
29
MR
OUT1•
DTR•
RTS•
OUT2•
NC
INTRPT
NC
A0
A1
A2
D6
D7
RCLK
N.C.
RX
TX
CS0
CS1
CS2
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Ei16C450
31
30
29
28
27
26
25
18
19
20
21
22
23
24
25
26
27
28
BAUDOUT
•
XTAL1
XTAL2
DOSTR•
DOSTR
VSS
NC
DISTR•
DISTR
DDIS
CSOUT
ADS•
IOR
IMP [ IMP, INC ]
