IMP1 232LP/LPS
Application Information
Supply Voltage Monitor
Reset Signal Polarity and Output Stage Structure
RESET is an active LOW signal. It is developed with an open
drain driver. If a pullup resistor is required, typical values are
10kΩ to 50kΩ.
RESET is an active High signal developed by a CMOS push-pull
output stage and is the logical opposite to RESET.
Trip Point Tolerance Selection
With TOL connected to V
CC
, RESET and RESET become active
whenever V
CC
falls below 4.5V. RESET and RESET become active
when V
CC
falls below 4.75V if TOL is connected to ground.
After V
CC
has risen above the trip point set by TOL, RESET and
RESET remain active for a minimum time period of 250ms.
On power-down, once V
CC
falls below the reset threshold RESET
stays LOW and is guaranteed to be 0.4V or less until V
CC
drops
below 1.2V. The active HIGH reset signal is valid down to a V
CC
level of 1.2V also.
t
R
V
CCTP
4.75V
PBRST
t
PB
t
PDLY
V
IL
V
CC
t
RST
t
RPU
RESET
V
OH
RESET
RESET
V
OH
V
OL
1232_08.eps
Tolerance
Select
TOL = V
CC
TOL = GND
TRIP Point Voltage (V)
Tolerance
10%
5%
Min
4.25
4.5
Nominal
4.37
4.62
Max
4.49
4.74
1232_t02.eps
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override the
internal trip point detection circuits and issue reset signals. The
pushbutton input is debounced and is normally pulled HIGH
through an internal 40kΩ resistor.
When PBRST is held LOW for the minimum time t
PB
, both resets
become active and remain active for approximately a minimum
time period of 250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses greater
than 20ms. No external pull-up resistor is required, since PBRST
is pulled HIGH by an internal 40kΩ resistor.
The PBRST can be driven from a TTL or CMOS logic line or short-
ed to ground with a mechanical switch.
4.25V
V
IH
V
OL
Figure 3. Timing Diagram: Pushbutton Reset
RESET
1232_05.eps
Figure 1. Timing Diagram: Power Up
1
t
F
V
CC
4.75V
V
CCTP
2
4.25V
3
4
5V
IMP1232LP/LPS
PBRST
TD
TOL
GND
V
CC
ST
RESET
RESET
8
7
6
5
µP
RESET
1232_06.eps
RESET
t
RPD
Figure 4. Application Circuit: Pushbutton Reset
RESET
V
OH
V
OL
1232_04.eps
Figure 2. Timing Diagram: Power Down
4
408-432-9100/www.impweb.com
©
1999 IMP, Inc.
IMP [ IMP, INC ]
