SOT-23 Power Supply reset Monitor With Complementary CMOS Output
Functional Description
The following designators 1~6 refer to the timing diagram below.
1. While the input voltage (V
IN
) is higher than the detect
voltage (V
DF
), the output voltage at V
OUT
pin equals the
input voltage at V
IN
pin.
2. When the input V
IN
voltage falls lower than V
DF
, V
OUT
drops near ground voltage.
3. If the input voltage decreases below the minimum operat-
ing voltage (V
MIN
), the V
OUT
output voltage will be undefined.
4. During an increase of the input voltage from the V
SS
voltage, V
OUT
is undefined at the voltage below V
MIN
.
Exceeding the V
MIN
level, the ouput stays at the ground
level (V
SS
) between the minimum operating voltage (V
MIN
)
and the detect release voltage (V
DR
).
5. If the input voltage increases more than V
DR
, the output
voltage at V
OUT
pin equals the input voltage at V
IN
pin.
6. The difference between V
DR
and V
DF
is the hysteresis
in the system.
Timing Diagram
INPUT VOLTAGE (V
IN
)
DETECT RELEASE VOLTAGE (V
DR
)
6
DETECT FAIL VOLTAGE (V
DF
)
MINIMUM OPERATING VOLTAGE (V
MIN
)
GROUND VOLTAGE (V
SS
)
OUTPUT VOLTAGE (V
OUT
)
GROUND VOLTAGE (V
SS
)
1
2
3
4
5
Impala Linear Corporation
ILC5062 1.3
(408) 574-3939
www.impalalinear.com
June 1999
3
IMPALA [ Impala Linear Corporation ]
