CoolSET™-F2
Functional Description
V
SoftS
5.3V
kHz
100
T
Soft-Start
V
FB
4.8V
t
f
OSC
65
21.5
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
V
IC
E2Axxxx
f
norm
f
standby
100kH
z
21.5kHz
ICE2Bxxxx
67kH
z
20kH
z
V
FB
Figure 15
Frequency Dependence
V
OUT
V
OUT
T
Start-Up
t
3.5
Current Limiting
t
Figure 14
Start Up Phase
3.4
Oscillator and Frequency
Reduction
Oscillator
3.4.1
There is a cycle by cycle current limiting realized by the
Current-Limit Comparator to provide an overcurrent
detection. The source current of the integrated
CoolMOS
TM
is sensed via an external sense resistor
R
Sense
. By means of R
Sense
the source current is
transformed to a sense voltage V
Sense
. When the
voltage V
Sense
exceeds the internal threshold voltage
V
csth
the Current-Limit-Comparator immediately turns
off the gate drive. To prevent the Current Limiting from
distortions caused by leading edge spikes a Leading
Edge Blanking is integrated at the Current Sense.
Furthermore a Propagation Delay Compensation is
added to support the immediate shut down of the
CoolMOS™ in case of overcurrent.
The oscillator generates a frequency f
switch
= 67kHz/
100kHz. A resistor, a capacitor and a current source
and current sink which determine the frequency are
integrated. The charging and discharging current of the
implemented oscillator capacitor are internally
trimmed, in order to achieve a very accurate switching
frequency. The ratio of controlled charge to discharge
current is adjusted to reach a max. duty cycle limitation
of D
max
=0.72.
3.5.1
Leading Edge Blanking
V
Sense
V
csth
t
LEB
= 220ns
3.4.2
Frequency Reduction
The frequency of the oscillator is depending on the
voltage at pin FB. The dependence is shown in Figure
15. This feature allows a power supply to operate at
lower frequency at light loads thus lowering the
switching losses while maintaining good cross
regulation performance and low output ripple. In case
of low power the power consumption of the whole
SMPS can now be reduced very effective. The minimal
reachable frequency is limited to 20kHz/21.5 kHz to
avoid audible noise in any case.
t
Figure 16
Leading Edge Blanking
Each time when CoolMOS™ is switched on a leading
spike is generated due to the primary-side
capacitances and secondary-side rectifier reverse
recovery time. To avoid a premature termination of the
switching pulse this spike is blanked out with a time
constant of t
LEB
= 220ns. During that time the output of
Version 2.8
13
30 Aug 2011
INFINEON [ INFINEON TECHNOLOGIES AG ]
