Electrical Characteristics
Frame Relationship in TE-Mode
The relationship between the S/T-interface and the IOM-interface in TE IOM-1 mode is shown
in figure 111. The pin X2 provides the M-bit during bits 0 through 23 and 26 through 31 of an
IOM-frame. It is recommended to sample the state of the M-bit with the falling edge of FSC 1.
At bit positions 24 and 25, the D-ECHO-bits appear according to the PEB 2085 functionality.
Mi+2
NT to TE
M
D L. F L.
B1
E D A F N
B2
E D
B1
E D S
B2
E D L. F L.
A
0
1
0
t ISD
t SID
FSC(O)
i
M
i+1
B2
i+1
i+1
i+2
M
M
E
M
E
M
X2(O)
B1
B1
B2
IDP0(O)
ITD03738
Figure 111
Frame Relationship in TE-Mode
Parameter
Symbol Limit Values
S-interface to IOM-delay
IOM-interface to S-delay
tSID
tISD
121 µs ± 300 ns1) ± 260 ns (jitter)
4 µs ± 300 ns1) ± 260 ns (jitter)
1)
Internal delays are dependent on temperature, VDD and fabrication parameters. The values may be reduced
after evaluation.
Semiconductor Group
271
INFINEON [ Infineon ]
