Functional Description
NT/LT-S Mode
DCL
FSC
PLL
MP
PP
PLL
MP: Receive clock for passive bus configuration
PP: Receive clock for point-to-point configuration
ITS02362
Figure 52
Clock System of the ISAC®-S in NT/LT-S Mode
TE and LT-T
In TE/LT-T applications, the transmit and receive bit clocks are derived, with the help of the
DPLL, from the S interface receive data stream. The received signal is sampled several times
inside the derived receive clock period, and a majority logic is used to additionally reduce bit
error rate in severe conditions (see chapter 2.5.4). The transmit frame is shifted by two bits
with respect to the received frame.
In TE mode the output clocks (DCL, FSC1 etc.) are synchronous to the S interface timing.
In LT-T mode the ISAC-S provides a 512-kHz clock, CP, derived from the 192-kHz receive line
clock with the DPLL. If necessary, this reference clock may be used to synchronize the central
system ("NT2") clock generator. The system timing is input over IOM interface bit and frame
clocks, DCL and FSC. The relative position of the S and IOM frame is arbitrary. Moreover, the
ISAC-S prevents a slip from occuring if the wander between the DCL and CP clocks does not
exceed a limit (The ISAC-S enables intermediate storage of: 3 × B
1
, 3 × B and four D-bits, for
2
phase difference and wander absorption). The maximum phase deviation between CP output
and DCL input may not exceed 1 µs per IOM frame (125 µs). In case a wander greater than
24 µs is exceeded, a warning is sent twice by the ISAC-S in the C/I channel ("slip").
If the analog test loop (TL3, see chapter 3.4) is closed, the 192-kHz line clock is internally
derived from DCL: therefore no slips can occur in this case.
Semiconductor Group
92
INFINEON [ Infineon ]
