IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Bits [15–4]—Reserved.
Bits [3–0]—DSA19–DSA16 → DMA Source Address High bits are driven onto a19–a16
during the read phase of a DMA transfer.
5.1.13 D1SRCL (0d0h) and D0SRCL (0c0h)
DMA SouRCe Address Low Register. The 16 bits of these registers are combined with the 4 bits
of the respective DMA Source Address High register to produce a 20-bit source address. They
are undefined at reset (see Table 29).
Table 29. DMA Source Address Low Register
15
14
13
12
11
10 9 8 7 6
DSA15–DSA0
5
4
3
2
1
0
Bits [15–0]—DSA15–DSA0 → DMA Source Address Low bits are placed onto a15–a0
during the read phase of a DMA transfer.
5.1.14 MPCS (0a8h)
MCS and PCS (MPCS) Auxiliary Register. Because this register controls more than one type of
chip select, it is unlike other chip select control registers. The MPCS register contains
information for mcs3_n–mcs0_n, pcs6_n–pcs5_n, and pcs3_n–pcs0_n.
The MPCS register also contains a bit that configures the pcs6_n–pcs5_n pins as either chip
selects or as alternate sources for the a2 and a1 address bits. Either a1/a2 or pcs6_n–pcs5_n are
selected to the exclusion of the other. When programmed for address bits, these outputs can be
used to provide latched address bits for a2 and a1.
The pcs6_n–pcs5_n pins are high and not active on processor reset. When the pcs6_n–pcs5_n
are configured as address pins, an access to the MPCS register causes them to activate. They do
not require corresponding access to the PACS register to be activated. The value of the MPCS
register is undefined at reset (see Table 30).
Table 30. MCS and PCS Auxiliary Register
15
1
14
13
12 11 10
M6–M0
9
8
7
EX
6
MS
5 4 3
Reserved
2
R2
1
0
R1–R0
Bit [15]—Reserved → Set to 1.
Bits [14–8]—M6–M0 mcs_n Block Size → These seven bits determine the total memory
block size for the mcs3_n–mcs0_n chip selects. The size is divided equally among them.
The relationship between M6–M0 and the size is shown below.
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