IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
4.2
Clock and Power Management
A phase-lock-loop (PLL) and a second programmable system clock output (clkoutb) are included
in the clock and power management unit. The internal clock is the same frequency as the crystal
but with a duty cycle of 45% to 55 %, as a worst case, generated by the PLL obviating the need
for an x2 external clock. A POR resets the PLL (see Figure 8).
C
1
x1
IA186EM/
IA188EM
Recommended
range of values for
C
1
and C
2
are:
C
1
= 15 pF ±20%
C
2
= 22 pF ±20%
C
2
x2
Crystal
Figure 8. Crystal Configuration
4.3
System Clocks
If required, the internal oscillator can be driven by an external clock source that should be
connected to x1, leaving x2 unconnected.
The clock outputs clkouta and clkoutb may be enabled or disabled individually (Power-Save
Control register (PDCON) Bits [11–8]). These clock control bits allow one clock output to run
at PLL frequency and the other to run at the power-save frequency (see Figure 9).
®
IA211050831-19
UNCONTROLLED WHEN PRINTED OR COPIED
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