IA186EM/IA188EM
8-Bit/16-Bit Microcontrollers
Data Sheet
February 25, 2011
Description:
When device is in halt state, the interrupt caused by a DMA completion will not
bring the CPU out of the halt state.
Workaround:
Use idle mode instead of halt.
Errata No. 6
Problem:
Does not clear the interrupt
request
bit for INT0 upon entering the ISR.
Description:
The interrupt bit for INT0 is not cleared until the interrupt routine is complete.
Workaround:
Do not rely on the bit to be cleared when nesting interrupts.
Errata No. 7
Problem:
How hardware handshaking for UARTs during a bus hold cycle is handled differently
between the AMD part and the Innovasic part.
Description:
In the AMD part, hardware handshaking works per the data sheet. The Innovasic
part will occasionally drive a handshake signal to the incorrect state during bus hold instead of
tristating the pin.
Workaround:
None. Avoid using hardware handshaking in conjunction with the bus hold
operation with the Innovasic part UARTs.
®
IA211050831-19
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Customer Support:
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
