IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
2.2
Pin Descriptions
2.2.1 a19/pio9, a18/pio8, a17/pio7, a16–a0—Address Bus (synchronous outputs with
tristate)
These pins are the system’s source of non-multiplexed I/O or memory addresses and occur a half
clkouta cycle before the multiplexed address/data bus (ad15–ad0 for the IA186EM or ao15–ao8
and ad7–ad0 for the IA188EM). The address bus is tristated during a bus hold or reset.
2.2.2 ad15–ad8 (IA186EM)—Address/data bus (level-sensitive synchronous inouts
with tristate)
These pins are the system’s source of time-multiplexed I/O or memory addresses and data. The
address function of these pins can be disabled (see bhe_n/aden_n pin description). If the address
function of these pins is enabled, the address will be present on this bus during t1 of the bus cycle
and data will be present during t2, t3, and t4 of the same bus cycle.
If whb_n is not active, these pins are tristated during t2, t3, and t4 of the bus cycle.
The address/data bus is tristated during a bus hold or reset.
These pins can be used to load the internal Reset Configuration register (RESCON, offset 0F6h)
with configuration data during a power-on reset (POR).
2.2.3 ad7–ad0—Address/Data bus (level-sensitive synchronous inouts with tristate)
These pins are the system’s source of time-multiplexed low-order byte of the addresses for I/O or
memory and 8-bit data. The low-order address byte will be present on this bus during t1 of the
bus cycle and the 8-bit data will be present during t2, t3, and t4 of the same bus cycle.
The address function of these pins can be disabled (see bhe_n/aden_n pin description).
If wlb_n (IA186EM) is not active, these pins are tristated during t2, t3, and t4 of the bus cycle.
The address/data bus is tristated during a bus hold or reset.
2.2.4 ao15–ao8 (IA188EM)—Address-only bus (level-sensitive synchronous outputs
with tristate)
The address-only bus will contain valid high-order address bits during the bus cycle (t1, t2, t3, and
t4) if the bus is enabled.
These pins are combined with ad7–ad0 to complete the multiplexed address bus and are tristated
during a bus hold or reset condition.
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