IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 88. Reset and Bus Hold Timing
a
a
No.
Name
Description
Min
Max
Reset and Bus Hold Timing Requirements
5
tCLAV
ad Address Valid Delay
ad Address Float Delay
res_n Setup Time
0
0
10
10
12
12
–
15 tCLAZ
57 tRESIN
58 tHVCL
hld Setup Time
–
Reset and Bus Hold Timing Responses
62 tCLHAV
63 tCHCZ
64 tCHCV
hlda Valid Delay
Command Lines Float Delay
Command Lines Valid Delay (after Float)
0
0
0
7
12
12
a
In nanoseconds.
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