IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
November 15, 2011
When Pulse Width Demodulation mode is enabled, tmrin0 is driven internally by
int2/inta0_n/pwd allowing for the pin to be configured as pio11.
2.2.43 tmrin1/pio0—Timer Input 1 (synchronous edge-sensitive input)
This signal may be either a clock or control signal for the internal timer 1. The timer is
incremented by the microcontroller after it synchronizes a rising edge of tmrin1. When not used,
tmrin1 must be tied high. When used as pio0, it is pulled up internally. When pulse width
demodulation mode is enabled, tmrin1 is driven internally by int2/inta0_n/pwd, allowing for the
pin to be configured as pio0.
2.2.44 tmrout0/pio10—Timer Output 0 (synchronous output)
This signal provides the system with a single pulse or a continuous waveform with a
programmable duty cycle. It is tristated during a bus hold or reset.
2.2.45 tmrout1/pio1—Timer Output 1 (synchronous output)
This signal provides the system with a single pulse or a continuous waveform with a
programmable duty cycle. It is tristated during a bus hold or reset.
2.2.46 txd0/pio22—Transmit Data 0 (asynchronous output)
This pin provides the system with asynchronous serial transmit data from serial port 0.
2.2.47 txd1/pio27—Transmit Data 1 (asynchronous output)
This pin provides the system with asynchronous serial transmit data from serial port 1.
2.2.48 ucs_n/once1_n—Upper Memory Chip Select (synchronous output)/ONCE Mode
Request 1 (input with internal pullup)
The ucs_n pin provides an indication that a memory access is in progress to the upper memory
block. The size of the upper memory block and its base address are programmable, with the size
adjustable up to 512 Kbytes. The ucs_n is held high during bus hold.
After reset, ucs_n is active for the 64-Kbyte memory range from F0000h to FFFFFh, which
includes the reset address at FFFF0h.
The once1_n pin (ON Circuit Emulation) and its companion pin, once0_n, define the
microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if
both are asserted low, the microcontroller starts in ONCE mode, otherwise it starts normally. In
ONCE mode, all pins are tristated and remain so until a subsequent reset. To prevent the
microcontroller from entering ONCE mode inadvertently, this pin has a weak pullup that is only
present during reset. This pin is not tristated during bus hold.
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