IA186ES/IA188ES
8-Bit/16-Bit Microcontrollers
Data Sheet
November 15, 2011
wait-state settings must agree with those for any overlapping chip selects as though they had
been configured as chip selects. This is true regardless of whether these pins are configured as
PIO and enabled (by writing to the MMCS and MPCS registers for the mcs_n chip selects and to
the PACS and MPCS registers for the pcs_n chip selects).
Even though pcs4_n is not available as an external pin, it has ready- and wait-state logic and
must therefore follow the rules for overlapping chip selects. By contrast, the pcs6_n and pcs5_n
have ready and wait-state logic that is disabled when they are configured as address bits a2
and a1, respectively.
If the chip-select-configuration rules are not followed, the processor may hang with the
appearance of waiting for a ready signal—even in a system where ready (ardy or srdy) is always
set to “1.”
4.11
Upper-Memory Chip Select
The ucs_n chip select is for the top of memory. On reset, the microcontroller begins fetching
and executing instructions at memory location FFFF0h, so upper memory is usually used for
instruction. To this end, ucs_n is active on reset and has a memory range of 64 Kbytes (F0000h
to FFFFFh) as default, along with external ready required and three wait states automatically
inserted. The lower boundary of ucs_n is programmable to provide ranges of 64 to 512 Kbytes.
4.12
Low-Memory Chip Select
The lcs_n chip select is for lower memory and may be configured for 8- or 16-bit accesses by the
AUXCON register. Because the interrupt vector table is at the bottom of memory beginning at
00000h, this pin is usually used for control data memory. Unlike ucs_n, this pin is inactive on
reset.
4.13
Midrange-Memory Chip Selects
There are four midrange chip selects, mcs3_n–mcs0_n, which may be used in a user-located
memory block. With some exceptions, the base address of the memory block may be located
anywhere in the 1-Mbyte memory address space. The memory spaces used by the ucs_n and
lcs_n chip selects are excluded, as are pcs6_n, pcs5_n, and pcs3_n–pcs0_n. If the pcs_n chip
selects are mapped to I/O space, the MCS address range can overlap the PCS address range.
The mcs0_n chip select may be programmed to be active over the entire MCS range, leaving the
mcs3_n–mcs1_n free for use as PIO pins.
The MCS may be configured for 8- or 16-bit accesses by the AUXCON register. The width of
the non-UCS/non-LCS memory ranges determines the MCS range bus width. The assertion of
the MCS outputs occurs with the same timing as the multiplexed AD address bus.
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