欢迎访问ic37.com |
会员登录 免费注册
发布采购

AM188ES-33VCW 参数 Datasheet PDF下载

AM188ES-33VCW图片预览
型号: AM188ES-33VCW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 154 页 / 1714 K
品牌: INNOVASIC [ INNOVASIC, INC ]
 浏览型号AM188ES-33VCW的Datasheet PDF文件第56页浏览型号AM188ES-33VCW的Datasheet PDF文件第57页浏览型号AM188ES-33VCW的Datasheet PDF文件第58页浏览型号AM188ES-33VCW的Datasheet PDF文件第59页浏览型号AM188ES-33VCW的Datasheet PDF文件第61页浏览型号AM188ES-33VCW的Datasheet PDF文件第62页浏览型号AM188ES-33VCW的Datasheet PDF文件第63页浏览型号AM188ES-33VCW的Datasheet PDF文件第64页  
IA186ES/IA188ES  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
November 15, 2011  
The current count of timer1 for INT2 and timer0 for INT4 should be inspected by the ISR to  
determine the pulse width. The timer count register should then be reset by the ISR in readiness  
for the next pulse.  
The timer count rate (one-fourth of the processor clock rate) determines the maximum resolution  
of the timers. To avoid the delay in servicing a timer interrupt in cases where the pulse width is  
short, the INT2 and INT4 request bits in the Interrupt Request register may be polled. In cases  
where the pulse width is greater than the maximum count of the timer, detection is achieved  
either by monitoring the Maximum Count (MC) bit of the respective timer or by enabling the  
timer interrupt requests by setting the INT bit in the respective Timer Mode and Control  
Register.  
4.25 Asynchronous Serial Ports  
There are two independent asynchronous serial ports that employ standard industry  
communication protocols in their implementation of full duplex, bi-directional data transfers.  
Functioning independently, either port may be the source or destination of DMA transfers.  
The following features are supported:  
Full-duplex data transfers  
7-, 8-, or 9-bit data transfers  
Odd, even, or no parity  
One or two stop bits  
Break characters of two lengths  
Error detection provided by parity, framing, or overrun errors  
Hardware handshaking achieved with the following selectable control signals:  
Clear to send (cts_n)  
Enable receiver request (enrx_n)  
Ready to send (rts_n)  
Ready to receive (rtr_n)  
DMA to and from the ports  
Each port has its own maskable interrupts  
9-bit multidrop protocol  
Each port has an independent baud-rate generator  
Maximum baud rate is 1/16 of the processor clock  
Transmit and receive lines are double buffered  
4.26 Programmable I/O  
Thirty-two pins are programmable as I/O signals (PIO). Table 15 presents them in both numeric  
and alphabetic order. Because programming a pin as a PIO disables its normal function, it  
should be done only if the normal function is not required. A PIO pin can be programmed as an  
®
IA211050902-19  
UNCONTROLLED WHEN PRINTED OR COPIED  
http://www.innovasic.com  
Customer Support:  
Page 60 of 154  
1-888-824-4184