IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Errata No. 5
Problem:
Bit 15 of RELREG (offset 0xFE) behaves differently than Intel device.
Description: For both 188 and 186 devices, an ESC opcode will generate a type 7 interrupt only
when RELREG[15] is a 0.
Workaround: Initialize RELREG[15] to 0 if a type 7 interrupt is desired.
Errata No. 6
Problem:
Enhanced mode makes bit 15 of RELREG (offset 0xFE) read-only.
Description: If the device comes out of reset in enhanced mode, RELREG[15] will be set to a
1.
Workaround: Avoid enhanced mode if a type 7 interrupt is desired.
Errata No. 7
Problem:
Sbus deasserts on the wrong edge of CLKOUT.
Description: The sbus goes inactive (high) at the end of a bus cycle on the falling edge of
CLKOUT. It should be on the rising edge of CLKOUT.
Workaround: None.
Errata No. 8
Problem:
Timer2 count register must be written to enable counting.
Description: If timer 2 count register is not explicitly written timer 2 will not count; this can
also prevent timers 0 & 1 from counting if timer 2 is used as a prescaler.
Workaround: Write timer 2 count register before enabling timer 2.
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