IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 77. Alphabetic Key to Waveform Parameters (Continued)
a
a
Min
10
Max
–
No. Name
tDVCL
Description
1
Data in Setup
19 tDXDL
58 tHVCL
53 tINVCH
54 tINVCL
86 tLCRF
23 tLHAV
10 tLHLL
13 tLLAX
61 tLOCK
84 tLRLL
57 tRESIN
85 tRFCY
29 tRHAV
59 tRHDX
28 tRHLH
26 tRLRH
den_n Inactive to dt/r_n Low
hld Setup Time
Peripheral Setup Time
drq Setup Time
lcs_n Inactive to rfsh_n Active Delay
ale High to Address Valid
ale Width
ad Address Hold from ale Inactive
Maximum PLL Lock Time
lcs_n Precharge Pulse Width
res_n Setup Time
0
10
10
10
–
–
–
–
–
–
–
–
0.5
–
–
–
–
–
–
–
–
2tCLCL
7.5
tCLCH-5
tCHCL
–
tCLCL+tCLCHH
10
rfsh_n Cycle Time
6tCLCL
tCLCL
0
tCLCH
tCLCL
10
tCLCH
tCLCL
tCLCH
2tCLCL
rd_n Inactive to ad Address Active
rd_n High to Data Hold on ad Bus
rd_n Inactive to ale High
rd_n Pulse Width
47 tSRYCL srdy Transition Setup Time
35 tWHDEX wr_n Inactive to den_n Inactive
34 tWHDX
33 tWHLH
32 tWLWH
–
–
–
–
Data Hold after wr_n
wr_n Inactive to ale High
wr_n Pulse Width
a
In nanoseconds.
Table 78. Numeric Key to Waveform Parameters
a
a
No. Name
Description
Min
10
0
0
0
0
0
0
Max
–
–
6
6
12
12
12
–
1
2
3
4
5
6
7
8
9
tDVCL Data in Setup
tCLDX Data in Hold
tCHSV Status Active Delay
tCLSH Status Inactive Delay
tCLAV
tCLAX
tCLDV Data Valid Delay
tCHDX Status Hold Time
tCHLH ale Active Delay
ad Address Valid Delay
Address Hold
0
0
8
10 tLHLL
11 tCHLL
12 tAVLL
13 tLLAX
ale Width
ale Inactive Delay
ad Address Valid to ale Low
ad Address Hold from ale Inactive
tCLCH-5
0
tCLCH
tCHCL
–
8
–
–
a
In nanoseconds.
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