IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 80. Write Cycle Timing
a
a
No.
Name
Description
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
0
–
–
General Timing Responses
3
4
5
6
8
9
tCHSV
tCLSH
tCLAV
tCLAX
tCHDX
tCHLH
Status Active Delay
Status Inactive Delay
ad Address Valid Delay
Address Hold
Status Hold Time
0
0
0
0
0
0
6
6
12
12
–
ale Active Delay
8
10 tLHLL
11 tCHLL
12 tAVLL
13 tLLAX
14 tAVCH
15 tCLAZ
16 tCLCSV
17 tCXCSX
18 tCHCSX
19 tDXDL
20 tCVCTV
21 tCVDEX
22 tCHCTV
23 tLHAV
99 tPLAL
ale Width
ale Inactive Delay
tCLCH-5
–
8
–
–
0
ad Address Valid to ale Low
ad Address Hold from ale Inactive
ad Address Valid to Clock High
ad Address Float Delay
mcs_n/pcs_n Inactive Delay
mcs_n/pcs_n Hold from Command Inactive
mcs_n/pcs_n Inactive Delay
den_n Inactive to dt/r_n Low
Control Active Delay 1
den_n Inactive Delay
tCLCH
tCHCL
0
0
0
–
12
12
–
12
–
10
9
10
–
tCLCH
0
0
0
0
0
Control Active Delay 2
ale High to Address Valid
pcs Low to ale Low
7.5
–
tCLCH
Write Cycle Timing Responses
30 tCLDOX
31 tCVCTX
32 tWLWH
33 tWHLH
34 tWHDX
35 tWHDEX
41 tDSHLH
65 tAVWL
67 tCHCSV
68 tCHAV
87 tAVBL
Data Hold Time
Control Inactive Delay
wr_n Pulse Width
wr_n Inactive to ale High
0
0
–
10
–
–
–
–
–
–
9
8
2tCLCL
tCLCH
tCLCL
tCLCH
tCLCH
Data Hold after wr_n
wr_n Inactive to den_n Inactive
ds_n Inactive to ale Inactive
a Address Valid to wr_n Low
clkouta High to lcs_n/usc_n Valid
clkouta High to a Address Valid
a Address Valid to whb_n/wlb_n Low
ds_n High to Data Invalid (Write)
tCLCL+tCHCL
0
0
tCHCL-1.5
0
tCHCL
tCLCL
98 tDSHDIW
a
In nanoseconds.
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