IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
When using the ad bus, DRAM refresh cycles are indicated by bhe_n/aden_n and ad0, both
being high. During refresh cycles, the a and ad busses may not have the same address during the
address phase of the ad bus cycle. This would necessitate the use of ad0 as a determinant for the
refresh cycle, rather than A0.
An additional signal is used for Pseudo-Static RAM (PSRAM) refreshes (see mcs3_n/rfsh_n pin
description), aden_n. There is a weak internal pullup on bhe_n/aden_n , eliminating the need for
an external pullup and reducing power consumption.
Holding aden_n high or letting it float during power-on reset (POR), passes control of the
address function of the ad bus (ad15–ad0) during LCS and UCS bus cycles from aden_n to the
Disable Address (DA) bit in LMCS and UMCS registers. When the address function is selected,
the memory address is placed on the a19–a0 pins.
When holding aden_n low during POR, both the address and data are driven onto the ad bus
independently of the DA bit setting. This pin is normally sampled on the rising edge of res_n
and the condition of s6 and uzi_n default to their normal functions.
2.2.8 clkouta—Clock Output A (synchronous output)
This pin is the internal clock output to the system. Bits [9–8] and Bits [2–0] of the System
Configuration (SYSCON) register control the output of this pin, which may be disabled, output
the PLL frequency, or output the power save frequency (internal processor frequency after
divisor). The clkouta may be used as a full-speed clock source in power-save mode. The AC
timing specifications that are clock-related refer to clkouta, which remains active during reset
and hold conditions.
2.2.9 clkoutb—Clock Output B (synchronous output)
This pin is an additional clock output to the system with and output delayed with respect to
clkouta. Bits [11–10] and Bits [2–0] of the SYSCON register control the output of this pin,
which may be disabled, output the PLL frequency, or may output the power save frequency
(internal processor frequency after divisor). The clkoutb may be used as a full-speed clock
source in power-save mode and remains active during reset and hold conditions.
2.2.10 cts0_n/enrx0_n/pio21—Clear-to-Send 0/Enable-Receive-Request 0 (both are
asynchronous inputs)
The cts0_n is the Clear-to-Send signal for asynchronous serial port 0, provided that Bit [4]
(ENRX0) in the AUXCON register is 0, and Bit [9] (FC) in the SP0CT register is 1. The cts0_n
controls the transmission of data from asynchronous serial port 0. When it is asserted, the
transmitter begins transmitting the next frame of data. When it is not asserted, the data to be
transmitted is held in the transmit register. This signal is checked only at the start of data frame
transmission.
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